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November 1992
Revised January 1999
7
4
AB
T5
43 Oct
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Regis
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3-ST
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s
1999 Fairchild Semiconductor Corporation
DS011508.prf
www.fairchildsemi.com
74ABT543
Octal Registered Transceiver with 3-STATE Outputs
General Description
The ABT543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
Features
s
Back-to-back registers for storage
s
Bidirectional data path
s
A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s
Separate controls for data flow in each direction
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for
SOIC, SSOP and TSSOP
Pin Descriptions
Order Number
Package Number
Package Description
74ABT543CSC M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT543CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT543CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
OEAB, OEBA
Output Enable Inputs
LEAB, LEBA
Latch Enable Inputs
CEAB, CEBA
Chip Enable Inputs
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
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2
74ABT543
Functional Description
The ABT543 contains two sets of D-type latches, with sep-
arate input and output controls for each. For data flow from
A to B, for example, the A to B Enable (CEAB) input must
be low in order to enter data from the A Port or take data
from the B Port as indicated in the Data I/O Control Table.
With CEAB low, a low signal on (LEAB) input makes the A
to B latches transparent; a subsequent low to high transi-
tion of the LEAB line puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both low, the B output buffers are
active and reflect the data present on the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Inputs
Latch Status
Output Buffers
CEAB
LEAB
OEAB
H
X
X
Latched
HIGH Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
HIGH Z
L
X
L
--
Driving
3
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7
4
AB
T5
43
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed but not tested.
Note 4: For 8-bit toggling. I
CCD
<
1.4 mA/MHz.
Note 5: Guaranteed, but not tested.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disable or Power-Off State
-
0.5V to
+
5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH Voltage
2.5
I
OH
=
-
3 mA, (A
n
, B
n
)
2.0
I
OH
=
-
32 mA, (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA, (A
n
, B
n
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A, (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Non-I/O Pins) (Note 3)
1
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V (Non-I/O Pins)
I
BVIT
Input HIGH Current
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 3)
-
1
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
10
A
0V5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEAB or CEAB
=
2V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0V5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEAB or CEAB
=
2V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
I
CCLH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
Outputs 3-STATE
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
Outputs Open, CEAB
(Note 5)
0.18
mA/MHz
Max
and OEAB
=
GND, CEBA
=
V
CC
, One Bit Toggling,
50% Duty Cycle, (Note 4)
www.fairchildsemi.com
4
74ABT543
DC Electrical Characteristics
(SOIC Package)
Note 6: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Packages)
AC Operating Requirements
(SOIC and SSOP Packages)
Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
C
L
=
50 pF,
R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.7
1.0
V
5.0
T
A
=
25
C (Note 6)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.2
-
0.8
V
5.0
T
A
=
25
C (Note 6)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
C (Note 7)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.7
V
5.0
T
A
=
25
C (Note 8)
V
ILD
Maximum LOW Level Dynamic Input Voltage
0.7
0.9
V
5.0
T
A
=
25
C (Note 8)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
1.5
3.1
4.8
1.5
4.8
ns
t
PHL
A
n
to B
n
or B
n
to A
n
1.5
4.8
1.5
4.8
t
PLH
Propagation Delay
t
PHL
LEAB to B
n
, LEBA to A
n
1.6
3.4
5.3
1.6
5.3
ns
OEBA or OEAB to A
n
or B
n
1.6
5.3
1.6
5.3
t
PZH
Enable Time
t
PZL
LEAB to B
n
, LEBA to A
n
1.5
3.6
5.8
1.5
5.8
ns
OEBA or OEAB to A
n
or B
n
1.5
5.8
1.5
5.8
t
PHZ
Disable Time
2.0
4.0
6.5
2.0
6.5
ns
t
PLZ
CEBA or CEAB to A
n
or B
n
2.0
6.5
2.0
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
1.5
1.5
ns
t
S
(L)
A
n
or B
n
to LEBA or LEAB
1.5
1.5
t
H
(H)
Hold Time, HIGH or LOW
1.0
1.0
ns
t
H
(L)
A
n
or B
n
to LEBA or LEAB
1.0
1.0
t
S
(H)
Setup Time, HIGH or LOW
1.5
1.5
ns
t
S
(L)
A
n
or B
n
to CEAB or CEBA
1.5
1.5
t
H
(H)
Hold Time, HIGH or LOW
1.3
1.3
ns
t
H
(L)
A
n
or B
n
to CEAB or CEBA
1.3
1.3
t
W
(L)
Pulse Width, LOW
3.0
3.0
ns
5
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7
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43
Extended AC Electrical Characteristics
(SOIC Package)
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 12: The 3-STATE delay times are dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet
Skew
(SOIC Package)
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). This specification is guaranteed but not tested.
Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
C
L
=
250 pF
8 Outputs Switching
1 Output Switching
8 Outputs Switching
(Note 9)
(Note 10)
(Note 11)
Min
Typ
Max
Min
Max
Min
Max
f
TOGGLE
Max Toggle Frequency
100
MHz
t
PLH
Propagation Delay
1.5
6.2
2.0
7.5
2.5
10.0
ns
t
PHL
A
n
to B
n
or B
n
to A
n
1.5
6.2
2.0
7.5
2.5
10.0
t
PLH
Propagation Delay
1.5
6.5
2.0
8.0
2.5
10.5
ns
t
PHL
LEAB to B
n
, LEBA to A
n
1.5
6.5
2.0
8.0
2.5
10.5
t
PZH
Output Enable Time
t
PZL
OEBA or OEAB to A
n
or B
n
1.5
7.5
2.0
8.5
2.5
11.0
ns
CEBA or CEAB to A
n
or B
n
1.5
7.5
2.0
8.5
2.5
11.0
t
PHZ
Output Disable Time
t
PLZ
OEBA or OEAB to A
n
or B
n
1.5
8.5
(Note 12)
(Note 12)
ns
CEBA or CEAB to A
n
or B
n
1.5
8.5
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
8 Outputs Switching
8 Outputs Switching
(Note 13)
(Note 14)
Max
Max
t
OSHL
Pin to Pin Skew
1.0
2.0
ns
(Note 15)
HL Transitions
t
OSLH
Pin to Pin Skew
1.3
2.0
ns
(Note 15)
LH Transitions
t
PS
Duty Cycle
2.0
4.0
ns
(Note 16)
LHHL Skew
t
OST
Pin to Pin Skew
2.0
4.0
ns
(Note 15)
LH/HL Transitions
t
PV
Device to Device Skew
2.5
4.5
ns
(Note 17)
LH/HL Transitions