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Электронный компонент: 74ABT646C

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1999 Fairchild Semiconductor Corporation
DS010978
www.fairchildsemi.com
April 1992
Revised November 1999
7
4
AB
T6
46
Oct
a
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r
an
sceive
rs and
Regi
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3-
ST
A
T
E O
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t
put
s
74ABT646
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
A and B output sink capability of 64 mA, source capabil-
ity of 32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74ABT646CSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide
74ABT646CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT646CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
A
0
A
7
Data Register A Inputs/3-STATE Outputs
B
0
B
7
Data Register B Inputs/3-STATE Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Select Inputs
OE
Output Enable Input
DIR
Direction Control Input
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2
74ABT646
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
FIGURE 2.
Storage from
Bus to Register
FIGURE 3.
Transfer from
Register to Bus
FIGURE 4.
Inputs
Data I/O
(Note 1)
Function
OE
DIR
CPAB
CPBA
SAB
SBA
A
0
A
7
B
0
B
7
H
X
H or L
H or L
X
X
Isolation
H
X
X
X
X
Input
Input
Clock A
n
Data into A Register
H
X
X
X
X
Clock B
n
Data into B Register
L
H
X
X
L
X
A
n
to B
n
--Real Time (Transparent Mode)
L
H
X
L
X
Input
Output Clock A
n
Data into A Register
L
H
H or L
X
H
X
A Register to B
n
(Stored Mode)
L
H
X
H
X
Clock A
n
Data into A Register and Output to B
n
L
L
X
X
X
L
B
n
to A
n
--Real Time (Transparent Mode)
L
L
X
X
L
Output
Input
Clock B
n
Data into B Register
L
L
X
H or L
X
H
B Register to A
n
(Stored Mode)
L
L
X
X
H
Clock B
n
Data into B Register and Output to A
n
3
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74
A
B
T
6
4
6
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74ABT646
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 4: Guaranteed but not tested.
Note 5: For 8-bit toggling, I
CCD
<
1.4 mA/MHz.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disable or
Power-Off State
-
0.5V to
+
5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH Voltage
2.5
I
OH
=
-
3 mA, (A
n
, B
n
)
2.0
I
OH
=
-
32 mA, (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
I
OL
=
64 mA, (A
n
, B
n
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A, (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Non-I/O Pins) (Note 4)
1
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current
7
A
Max
V
IN
=
7.0V (Non-I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 4)
-
1
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
10
A
0V5.5V V
OUT
=
2.7V (A
n
, B
n
); OE
=
2.0V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0V5.5V V
OUT
=
0.5V (A
n
, B
n
); OE
=
2.0V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
I
CCH
Power Supply Current
250
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
Outputs 3-STATE; All Others GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V
All Other Outputs at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
Outputs OPEN
(Note 4)
0.18
mA/MHz
Max
OE and DIR
=
GND,
Non-I/O
=
GND or V
CC
(Note 5)
One Bit toggling, 50% duty cycle
5
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74
A
B
T
6
4
6
DC Electrical Characteristics
Note 6: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 8: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
AC Operating Requirements
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.6
0.8
V
5.0
T
A
=
25
C (Note 6)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.2
-
0.9
V
5.0
T
A
=
25
C (Note 6)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
(Note 7)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V
5.0
T
A
=
25
C (Note 8)
V
ILD
Maximum LOW Level Dynamic Input Voltage
0.8
0.5
V
5.0
T
A
=
25
C (Note 8)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
200
200
200
MHz
t
PLH
Propagation Delay
1.7
3.0
5.6
2.2
8.8
1.7
5.6
ns
t
PHL
Clock to Bus
1.7
3.4
5.6
1.7
8.8
1.7
5.6
t
PLH
Propagation Delay
1.5
2.6
4.8
1.5
7.9
1.5
4.8
ns
t
PHL
Bus to Bus
1.5
3.0
4.8
1.5
7.9
1.5
4.8
t
PLH
Propagation Delay
1.5
3.0
5.9
1.5
8.1
1.5
5.9
ns
t
PHL
SBA or SAB to A
n
to B
n
1.5
3.4
5.9
1.5
8.9
1.5
5.9
t
PZH
Enable Time
1.5
3.2
6.3
1.0
7.3
1.5
6.3
ns
t
PZL
OE to A
n
or B
n
1.5
3.5
6.3
1.9
8.8
1.5
6.3
t
PHZ
Disable Time
1.5
3.7
6.0
1.5
9.3
1.5
6.0
ns
t
PLZ
OE to A
n
or B
n
1.5
3.2
6.0
1.5
9.3
1.5
6.0
t
PZH
Enable Time
1.5
3.4
6.3
1.0
7.7
1.5
6.3
ns
t
PZL
DIR to A
n
or B
n
1.5
3.7
6.3
2.2
9.5
1.5
6.3
t
PHZ
Disable Time
1.5
3.8
6.0
1.5
8.7
1.5
6.0
ns
t
PLZ
DIR to A
n
or B
n
1.5
3.2
6.0
1.5
9.2
1.5
6.0
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH
1.5
1.5
3.0
1.5
ns
t
S
(L)
or LOW Bus to Clock
t
H
(H)
Hold Time, HIGH
1.0
1.0
1.0
1.0
ns
t
H
(L)
or LOW Bus to Clock
t
W
(H)
Pulse Width,
3.0
3.0
4.0
3.0
ns
t
W
(L)
HIGH or LOW