2000 Fairchild Semiconductor Corporation
DS500295
www.fairchildsemi.com
August 1999
Revised November 2000
7
4
AC
1
6244
74ACT16244 16-
Bit
Buf
f
er
/Li
n
e D
r
ive
r
wi
th 3-
S
T
A
T
E
Out
puts
74AC16244 74ACT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The AC16244 and ACT16244 contain sixteen non-inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Each
nibble has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation.
Features
s
Separate control logic for each byte and nibble
s
16-bit version of the AC244/ACT244
s
Outputs source/sink 24 mA
s
ACT16244 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74AC16244SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74ACT16244SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74ACT16244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
I
0
- I
15
Inputs
O
0
- 0
15
Outputs
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2
74AC16244
74ACT16244
Functional Description
The AC16244 and ACT16244 contain sixteen non-inverting
buffers with 3-STATE standard outputs. The device is nib-
ble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The
3-STATE outputs are controlled by an Output Enable (OE
n
)
input for each nibble. When OE
n
is LOW, the outputs are in
2-state mode. When OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Truth Tables
L
=
LOW Voltage Level
H
=
HIGH Voltage Level
X
=
Immaterial
Z
=
High Impedance
Logic Diagram
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
3
I
8
I
11
O
8
O
11
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
4
I
12
I
15
O
12
O
15
L
L
L
L
H
H
H
X
Z
3
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7
4
AC
1
6244
74ACT16244
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 4: Maximum test duration 2.0 millisecond; one output loaded at a time.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin
50 mA
Junction Temperature
+
140
C
Storage Temperature
-
65
C to
+
150
C
Supply Voltage (V
CC
)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
AC Devices
V
IN
from 30% to 70%
V
CC
@ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate (
V/
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Input Voltage
3.0
1.5
2.1
2.1
V
V
OUT
=
0.1V
4.5
2.25
3.15
3.15
or V
CC
-
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Input Voltage
3.0
1.5
0.9
0.9
V
V
OUT
=
0.1V
4.5
2.25
1.35
1.35
or V
CC
-
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Output Voltage
3.0
2.99
2.9
2.9
V
I
OUT
=
-
50
A
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
I
OH
=
-12 mA
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum LOW Output Voltage
3.0
0.002
0.1
0.1
V
I
OUT
=
50
A
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
I
OL
=
12 mA
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 2)
I
OZ
Maximum 3-STATE Leakage Current
5.5
0.50
5.0
A
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
I
IN
Maximum Input Leakage Current (Note 3)
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
CC
Max Quiescent Supply Current (Note 3)
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 4)
5.5
-
75
mA
V
OHD
=
3.85V Min
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4
74AC16244
74ACT16244
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; thresholds associated with output under test.
Note 6: Maximum test duration 2.0 millisecond; one output loaded at a time.
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Input Voltage
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW Input Voltage
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH Output Voltage
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 5)
V
OL
Maximum LOW Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OH
=
24 mA
5.5
0.36
0.44
I
OH
=
24 mA (Note 5)
I
OZ
Maximum 3-STATE Leakage Current
5.5
0.5
5.0
A
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
Max Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 6)
-
75
mA
V
OHD
=
3.85V Min
5
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7
4
AC
1
6244
74ACT16244
AC Electrical Characteristics for AC
Note 7: Voltage Range 5.0 is 5.0V
0.5V.
Voltage Range 3.3 is 3.3V
0.3V.
AC Electrical Characteristics for ACT
Note 8: Voltage Range 5.0 is 5.0V
0.5V.
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 7)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.3
2.0
6.3
9.4
2.0
10.8
ns
Data to Output
5.0
1.6
4.6
6.5
1.6
7.1
t
PHL
Propagation Delay
3.3
2.4
5.7
10.7
2.4
11.8
ns
Data to Output
5.0
2.0
4.3
7.0
2.0
7.9
t
PZH
Output Enable Time
3.3
2.2
6.2
10
2.2
11.5
ns
5.0
1.7
4.6
6.7
1.7
7.5
t
PZL
Output Enable Time
3.3
2.9
6.4
13.0
2.9
14.6
ns
5.0
2.2
4.7
8.1
2.2
9.0
t
PHZ
Output Disable Time
3.3
3.1
5.5
8.4
3.1
9.1
ns
5.0
1.9
3.9
7.8
1.9
8.4
t
PLZ
Output Disable Time
3.3
2.4
4.7
8.1
2.4
8.8
ns
5.0
1.7
3.6
7.2
1.7
7.6
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
3.0
5.2
7.3
3.0
7.8
ns
t
PHL
Data to Output
2.5
4.8
6.8
2.5
7.3
t
PZH
Output Enable
5.0
2.5
5.0
7.4
2.5
7.9
ns
t
PZL
Time
2.7
4.6
7.5
2.7
8.0
t
PHZ
Output Disable
5.0
2.3
5.0
7.9
2.3
8.2
ns
t
PLZ
Time
2.0
4.6
7.4
2.0
7.9
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Pin Capacitance
4.5
pF
V
CC
=
5.0V
C
OUT
Output Pin Capacitance
12
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
74AC16244
35
pF
V
CC
=
5.0V
74ACT16244
30
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6
74AC16244
74ACT16244
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Package Number MS48A
7
www.fairchildsemi.com
7
4
AC
1
6244
74ACT16244 16-
Bit
Buf
f
er
/Li
n
e D
r
ive
r
wi
th 3-
S
T
A
T
E
Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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