2000 Fairchild Semiconductor Corporation
DS010156
www.fairchildsemi.com
November 1988
Revised September 2000
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AC
T8
41
10-
Bit
T
r
anspar
ent Lat
c
h
wi
th 3-ST
A
T
E
Out
puts
74ACT841
10-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ACT841 is a 10-bit transparent
latch, a 10-bit version of the ACT373.
Features
s
ACT841 has TTL-compatible inputs
s
Outputs source/sink 24 mA
s
Non-inverting 3-STATE outputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACT841SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT841MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT841SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
D
0
D
9
Data Inputs
O
0
O
9
3-STATE Outputs
OE
Output Enable
LE
Latch Enable
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74ACT841
Functional Description
The ACT841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Internal
Output
Function
OE
LE
D
Q
O
X
X
X
X
Z
High Z
H
H
L
L
Z
High Z
H
H
H
H
Z
High Z
H
L
X
NC
Z
Latched
L
H
L
L
L
Transparent
L
H
H
H
H
Transparent
L
L
X
NC
NC
Latched
3
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Input Voltage (V
I
)
-
0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Junction Temperature (T
J
)
PDIP
140
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 2)
I
IN
Maximum Input
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
Leakage Current
I
OZ
Maximum 3-STATE
5.5
0.5
5.0
A
V
I
=
V
IL
, V
IH
Leakage Current
V
O
=
V
CC
, GND
I
CCT
Maximum
5.5
0.6
1.5
A
V
I
=
V
CC
-
2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 3)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
Maximum Quiescent
5.5
8.0
80.0
A
V
IN
=
V
CC
Supply Current
or GND
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74ACT841
AC Electrical Characteristics
Note 4: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
Note 5: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 4)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
2.0
5.5
9.5
2.0
10.0
ns
D
n
to O
n
t
PHL
Propagation Delay
5.0
2.0
5.5
9.5
2.0
10.0
ns
D
n
to O
n
t
PLH
Propagation Delay
5.0
2.0
5.5
9.0
2.0
10.0
ns
LE to O
n
t
PHL
Propagation Delay
5.0
2.0
5.5
9.0
2.0
10.0
ns
LE to O
n
t
PZH
Output Enable Time
5.0
2.0
5.5
9.5
2.0
10.5
ns
OE to O
n
t
PZL
Output Enable Time
5.0
2.0
5.5
9.5
2.0
10.5
ns
OE to O
n
t
PHZ
Output Disable Time
5.0
2.0
6.0
10.5
2.0
11.0
ns
OE to O
n
t
PLZ
Output Disable Time
5.0
2.0
6.0
10.5
2.0
11.0
ns
OE to O
n
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 5)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
-
0.5
0.5
1.0
ns
D
n
to LE
t
H
Hold Time, HIGH or LOW
5.0
0.5
2.0
2.0
ns
D
n
to LE
t
W
LE Pulse Width, HIGH
5.0
2.0
3.5
3.5
ns
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
OPEN
C
PD
Power Dissipation Capacitance
44
pF
V
CC
=
5.0V
5
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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