June 1991
Revised January 1999
7
4
A
C
TQ16646
16-
Bit
T
r
anscei
ver/
R
egi
ster
wi
th
3-ST
A
T
E Out
puts
1999 Fairchild Semiconductor Corporation
DS010937.prf
www.fairchildsemi.com
74ACTQ16646
16-Bit Transceiver/Register with 3-STATE Outputs
General Description
The ACTQ16646 contains sixteen non-inverting bidirec-
tional registered bus transceivers providing multiplexed
transmission of data directly from the input bus or from the
internal storage registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. The DIR inputs determine the direction of data flow
through the device. The CPAB and CPBA inputs load data
into the registers on the LOW-to-HIGH transition. The
ACTQ16646 utilizes Fairchild Quiet Series
TM
technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
TM
features
GTO
TM
output control and undershoot corrector for superior
performance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data transfers
s
Separate control logic for each byte
s
16-bit version of the ACTQ646
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for
SSOP and TSSOP
FACT
TM
, Quiet Series
TM
, FACT Quiet Series
TM
and GTO
TM
are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACTQ16646SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACTQ16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74A
CTQ16646
Function Table
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition.
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins.
Real Time Transfer
A-Bus to B-Bus
Real Time Transfer
B-Bus to A-Bus
Storage from
Bus to Register
Transfer from
Register to Bus
Inputs
Data I/O (Note 1)
Output Operation Mode
G
1
DIR
1
CPAB
1
CPBA
1
SAB
1
SBA
1
A
07
B
07
H
X
H or L
H or L
X
X
Isolation
H
X
X
X
X
Input
Input
Clock An Data into A Register
H
X
X
X
X
Clock Bn Data Into B Register
L
H
X
X
L
X
An to Bn--Real Time (Transparent Mode)
L
H
X
L
X
Input
Output
Clock An Data to A Register
L
H
H or L
X
H
X
A Register to Bn (Stored Mode)
L
H
X
H
X
Clock An Data into A Register and Output to Bn
L
L
X
X
X
L
Bn to An--Real Time (Transparent Mode)
L
L
X
X
L
Output
Input
Clock Bn Data into B Register
L
L
X
H or L
X
H
B Register to An (Stored Mode)
L
L
X
X
H
Clock Bn into B Register and Output to An
3
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A
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TQ16646
Logic Diagram
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4
74A
CTQ16646
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms; one output loaded at a time.
Note 5: Worst case package.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin
50 mA
Storage Temperature
-
65
C to
+
150
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 3)
V
OL
Maximum LOW
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
= 24 mA
5.5
0.36
0.44
I
OL
= 24 mA (Note 3)
I
OZT
Maximum I/O
5.5
0.5
5.0
A
V
IN
=
V
IL
, V
IH
Leakage Current
V
O
=
V
CC
, GND
I
IN
Maximum Input
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
Leakage Current
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
Max Quiescent
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
Supply Current
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 4)
-
75
mA
V
OHD
=
3.85V Min
V
OLP
Quick Output
5.0
0.5
0.8
V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 6)(Note 7)
V
OLV
Quick Output
5.0
-
0.5
-
0.8
V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 6)(Note 7)
V
OHP
Maximum
5.0
V
OH
+
1.0
V
OH
+
1.5
V
Figure 1, Figure 2
Overshoot
(Note 5)(Note 7)
V
OHV
Minimum
5.0
V
OH
-
1.0
V
OH
-
1.8
V
Figure 1, Figure 2
V
CC
Droop
(Note 5)(Note 7)
V
IHD
Minimum HIGH Dynamic
5.0
1.7
2.0
V
(Note 5)(Note 8)
Input Voltage Level
V
ILD
Maximum LOW Dynamic
5.0
1.2
0.8
V
(Note 5)(Note 8)
Input Voltage Level
5
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7
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TQ16646
DC Electrical Characteristics
(Continued)
Note 6: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched LOW and one output held LOW.
Note 7: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched HIGH and one output held HIGH.
Note 8: Maximum number of data inputs (n) switching. (n
-
1) inputs switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (V
ILD
).
AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5.0V
0.5V.
AC Operating Requirements
Note 10: Voltage Range 5.0 is 5.0V
0.5V.
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
t
PHL
Propagation Delay
5.0
4.6
6.9
9.4
3.6
10.1
ns
t
PLH
Clock to Bus
4.3
6.5
8.9
3.3
9.7
t
PHL
Propagation Delay
5.0
4.0
6.2
8.5
2.9
9.2
ns
t
PLH
Bus to Bus
4.1
6.4
8.6
3.2
9.3
t
PHL
Propagation Delay
5.0
4.0
6.4
8.9
3.1
9.6
ns
t
PLH
Select to Bus
4.2
6.7
9.5
3.2
10.4
(w/An or Bn HIGH or LOW)
t
PZL
Enable Time
5.0
5.3
7.8
10.5
3.8
11.4
ns
t
PZH
G to An/Bn
4.6
6.9
9.4
3.3
10.2
t
PLZ
Disable Time
5.0
3.0
5.5
8.1
2.3
8.6
ns
t
PHZ
G to An/Bn
3.4
5.7
8.3
2.6
8.6
t
PZL
Enable Time
5.0
5.1
8.2
11.8
4.3
12.7
ns
t
PZH
DIR to An/Bn
4.6
7.5
10.8
3.7
11.7
t
PLZ
Disable Time
5.0
2.9
5.8
9.2
2.0
9.8
ns
t
PHZ
DIR to An/Bn
3.4
6.1
9.2
2.5
9.7
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 10)
Guaranteed Minimum
t
S
Setup Time, H or L
5.0
3.0
3.0
ns
Bus to Clock
t
H
Hold Time, H or L
5.0
1.5
1.5
ns
Bus to Clock
t
W
Clock Pulse Width
5.0
4.0
4.0
ns
H or L
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