1999 Fairchild Semiconductor Corporation
DS010953
www.fairchildsemi.com
September 1991
Revised November 1999
7
4
AC
TQ188
23
18-
Bit
D-
T
y
pe Fli
p
-Fl
op w
i
th 3-
S
T
A
T
E O
u
t
puts
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild's Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
fea-
tures GTO
output control and undershoot corrector for
superior performance.
Features
s
Utilizes Fairchild's FACT Quiet Series technology
s
Broadside pinout allows for easy board layout
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
FACT
, Quiet Series
, FACT Quiet Series
, and GTO
are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACTQ18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACTQ18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
CLR
n
Clear (Active LOW)
EN
n
Clock Enable (Active LOW)
CP
n
Clock Pulse Input
I
0
I
17
Inputs
O
0
O
17
Outputs
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2
74ACTQ18823
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-trig-
gered flip-flops. These have 3-STATE outputs for bus sys-
tems organized with inputs and outputs on opposite sides.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. The
following description applies to each byte. The buffered
clock (CP
n
) and buffered Output Enable (OE
n
) are com-
mon to all flip-flops within that byte. The flip-flops will store
the state of their individual D inputs that meet set-up and
hold time requirements on the LOW-to-HIGH CP
n
transi-
tion. With OE
n
LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the impedance state. Operation of the OE
n
input does not
affect the state of the flip-flops. In addition to the Clock and
Output Enable pins, there are Clear (CLR
n
) and Clock
Enable (EN
n
) pins. These devices are ideal for parity bus
interfacing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Note 1: The table represents the logic for one byte. The two bytes are independent of each other and function identically.
Inputs
Internal
Output
Function
OE
CLR
EN
CP
I
n
Q
O
n
H
X
L
L
L
Z
High Z
H
X
L
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
Load
L
H
L
L
L
L
Load
L
H
L
H
H
H
Load
3
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7
4
AC
TQ188
23
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
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4
74ACTQ18823
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Worst case package.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched LOW and one output held LOW.
Note 7: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched HIGH and one output held HIGH.
Note 8: Maximum number of data inputs (n) switching. (n
-
1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
).
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
Per Output Pin
50 mA
Junction Temperature
PDIP/SOIC
+
140
C
Storage Temperature
-
65
C to
+
150
C
ESD Last Passing Voltage (Min)
4000V
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 3)
V
OL
Maximum LOW
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 3)
I
OZ
Maximum 3-STATE
5.5
0.5
5.0
A
V
I
=
V
IL
, V
IH
Leakage Current
V
O
=
V
CC
, GND
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
Maximum Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 4)
-
75
mA
V
OHD
=
3.85V Min
V
OLP
Quiet Output Maximum Dynamic V
OL
5.0
0.5
0.8
V
(Note 6)(Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0
-
0.5
-
0.8
V
(Note 6)(Note 7)
V
OHP
Maximum Overshoot
5.0
V
OH
+
1.0
V
OH
+
1.5
V
(Note 5)(Note 7)
V
OHV
Minimum V
CC
Droop
5.0
V
OH
-
1.0
V
OH
-
1.8
V
(Note 5)(Note 7)
V
IHD
Minimum High Voltage Level
5.0
1.7
2.0
V
(Note 5)(Note 8)
V
ILD
Maximum Low Dynamic Input Voltage Level
5.0
1.2
1.2
V
(Note 5)(Note 8)
5
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7
4
AC
TQ188
23
AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5.0V
0.5V.
AC Operating Requirements
Note 10: Voltage Range 5.0 is 5.0V
0.5V.
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
5.0
100
90
MHz
Frequency
t
PHL
Propagation Delay
5.0
2.0
9.0
2.0
9.5
ns
t
PLH
CP
n
to O
n
2.0
9.0
2.0
9.5
t
PHL
Propagation Delay
5.0
2.0
9.0
2.0
9.5
ns
CLR
n
to O
n
t
PZL
Output Enable Time
5.0
2.0
9.0
2.0
10.0
ns
t
PZH
2.0
9.0
2.0
10.0
t
PLZ
Output Disable Time
5.0
1.5
7.0
1.5
7.5
ns
t
PHZ
1.5
8.0
1.5
8.5
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 10)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW,
5.0
3.0
3.0
ns
Input to Clock
t
H
Hold Time, HIGH or LOW,
5.0
1.5
1.5
ns
Input to Clock
t
S
Setup Time, HIGH or LOW,
5.0
3.0
3.0
ns
Enable to Clock
t
H
Hold Time, HIGH or LOW,
5.0
1.5
1.5
ns
Enable to Clock
t
W
CP
n
Pulse Width,
5.0
4.0
4.0
ns
HIGH or LOW
t
W
CLR
n
Pulse Width,
5.0
4.0
4.0
ns
HIGH or LOW
t
REC
Recovery Time,
5.0
6.0
6.0
ns
CLR
n
to CP
n
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6
74ACTQ18823
Extended AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (il.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 15: The Output Disable Time is dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
Com
T
A
=
-
40
C to
+
85
C
C
L
=
50 pF
V
CC
=
Com
16 Outputs Switching
C
L
=
250 pF
(Note 12)
(Note 13)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.2
6.5
7.6
7.0
9.8
ns
t
PHL
CP
n
to O
n
5.3
6.5
7.8
6.8
10.0
t
PHL
Propagation Delay
4.8
5.3
6.2
5.2
7.5
ns
CLR
n
to O
n
t
PZH
Output Enable Time
4.2
4.8
6.5
(Note 14)
ns
t
PZL
4.4
5.3
6.0
t
PHZ
Output Disable Time
3.5
4.2
4.8
(Note 15)
ns
t
PZL
4.6
5.2
6.0
t
OSHL
Pin to Pin Skew
1.0
ns
(Note 11)
CP
n
to O
n
t
OSLH
Pin to Pin Skew
1.0
ns
(Note 11)
CP
n
to O
n
t
OSHL
Pin to Pin Skew
1.0
ns
(Note 11)
CLR
n
to Output
t
OST
Pin to Pin Skew
1.5
ns
(Note 11)
CP
n
to Output
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Pin Capacitance
4.5
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
95
pF
V
CC
=
5.0V
7
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7
4
AC
TQ188
23
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
V
OHV
and V
OLP
are measured with respect to ground reference.
Input pulses have the following characteristics: f
=
1 MHz, t
r
=
3 ns,
t
f
=
3 ns, skew
<
150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillator steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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8
74ACTQ18823
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS56A
9
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7
4
AC
TQ188
23
18-
Bit
D-
T
y
pe Fli
p
-Fl
op w
i
th 3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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