2005 Fairchild Semiconductor Corporation
DS010236
www.fairchildsemi.com
July 1989
Revised March 2005
7
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AC
Q245 74AC
T
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Qui
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Oct
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74ACQ245 74ACTQ245
Quiet Series
Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The ACQ/ACTQ245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus-
oriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirec-
tional transceiver. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series
fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard ACT245
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
, Quiet Series
, FACT Quiet Series
, and GTO
are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package
Package Description
Number
74ACQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACQ245SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACTQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACTQ245SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ245QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
74ACTQ245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ACTQ245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ245MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACTQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A
0
A
7
Side A 3-STATE Inputs or 3-STATE Outputs
B
0
B
7
Side B 3-STATE Inputs or 3-STATE Outputs
Inputs
Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
3
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AC
Q245
74AC
T
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Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
V
I
V
CC
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to V
CC
0.5V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
DC Latch-Up Source or
Sink Current
r
300 mA
Junction Temperature (T
J
)
PDIP
140
q
C
Supply Voltage (V
CC
)
ACQ
2.0V to 6.0V
ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Minimum Input Edge Rate
'
V/
'
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
125 mV/ ns
Minimum Input Edge Rate
'
V/
'
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
3.0
1.5
2.1
2.1
V
OUT
0.1V
Input Voltage
4.5
2.25
3.15
3.15
V
or V
CC
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Level
3.0
1.5
0.9
0.9
V
OUT
0.1V
Input Voltage
4.5
2.25
1.35
1.35
V
or V
CC
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
3.0
2.56
2.46
I
OH
12 mA
4.5
3.86
3.76
V
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 3)
V
OL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
3.0
0.36
0.44
I
OL
12 mA
4.5
0.36
0.44
V
I
OL
24 mA
5.5
0.36
0.44
I
OL
24 mA (Note 3)
I
IN
Maximum Input
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
(Note 5)
Leakage Current
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 4)
5.5
75
mA
V
OHD
3.85V Min
I
CC
Maximum Quiescent
5.5
4.0
40.0
P
A
V
IN
V
CC
(Note 5)
Supply Current
or GND
I
OZT
Maximum I/O
V
I
(OE)
V
IL
, V
IH
Leakage Current
5.5
r
0.3
r
3.0
P
A
V
I
V
CC
, GND
V
O
V
CC
, GND
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DC Electrical Characteristics for ACQ
(Continued)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 6: DIP package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND.
Note 8: Max number of Data Inputs (n) switching. (n
1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
1 MHz.
DC Electrical Characteristics for ACTQ
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
Note 11: DIP package.
Note 12: Max number of outputs defined as (n). n
1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 13: Max number of Data Inputs (n) switching. (n
1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
1 MHz.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
OLP
Quiet Output
5.0
1.1
1.5
V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 6)(Note 7)
V
OLV
Quiet Output
5.0
0.6
1.2
V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 6)(Note 7)
V
IHD
Minimum HIGH Level
5.0
3.1
3.5
V
(Note 6)(Note 8)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0
1.9
1.5
V
(Note 6)(Note 8)
Dynamic Input Voltage
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
50
P
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
24 mA
5.5
4.86
4.76
I
OH
24 mA (Note 9)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
50
P
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
24 mA
5.5
0.36
0.44
I
OL
24 mA (Note 9)
I
IN
Maximum Input Leakage Current
5.5
r
0.1
r
1.0
P
A
V
I
V
CC
, GND
I
OZT
Maximum 3-STATE
5.5
r
0.3
r
3.0
P
A
V
I
V
IL
, V
IH
Leakage Current
V
O
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
V
CC
2.1V
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
1.65V Max
I
OHD
Output Current (Note 10)
5.5
75
mA
V
OHD
3.85V Min
I
CC
Maximum Quiescent Supply Current
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
V
OLP
Quiet Output
5.0
1.1
1.5
V
Figure 1, Figure 2
Maximum Dynamic V
OL
(Note 11)(Note 12)
V
OLV
Quiet Output
5.0
0.6
1.2
V
Figure 1, Figure 2
Minimum Dynamic V
OL
(Note 11)(Note 12)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
5.0
1.9
2.2
V
(Note 11)(Note 13)
V
ILD
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 11)(Note 13)
5
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AC
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74AC
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2
4
5
AC Electrical Characteristics for ACQ
Note 14: Voltage Range 5.0 is 5.0V
r
0.5V
Voltage Range 3.3 is 3.3V
r
0.3V
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Electrical Characteristics for ACTQ
Note 16: Voltage Range 5.0 is 5.0V
r
0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Symbol
Parameter
(V)
C
L
50 pF
C
L
50 pF
Units
(Note 14)
Min
Typ
Max
Min
Max
t
PHL
Propagation Delay
3.3
2.0
7.5
10.0
2.0
10.5
ns
t
PLH
Data to Output
5.0
1.5
5.0
6.5
1.5
7.0
t
PZL
Output Enable Time
3.3
3.0
8.5
13.0
3.0
13.5
ns
t
PZH
5.0
2.0
6.0
8.5
2.0
9.0
t
PHZ
Output Disable Time
3.3
1.0
8.5
14.5
1.0
15.0
ns
t
PLZ
5.0
1.0
7.5
9.5
1.0
10.0
t
OSHL
Output to Output Skew (Note 15)
3.3
1.0
1.5
1.5
ns
t
OSLH
Data to Output
5.0
0.5
1.0
1.0
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Symbol
Parameter
(V)
C
L
50 pF
C
L
50 pF
Units
(Note 16)
Min
Typ
Max
Min
Max
t
PHL
Propagation Delay
5.0
1.5
5.5
7.0
1.5
7.5
ns
t
PLH
Data to Output
t
PZL
, t
PZH
Output Enable Time
5.0
2.0
7.0
9.0
2.0
9.5
ns
t
PHZ
, t
PLZ
Output Disable Time
5.0
1.0
8.0
10.0
1.0
10.5
ns
t
OSHL
Output to Output Skew (Note 17)
5.0
0.5
1.0
1.0
ns
t
OSLH
Data to Output
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
OPEN
C
I/O
Input/Output Capacitance
15
pF
V
CC
5.0V
C
PD
Power Dissipation Capacitance
80.0
pF
V
CC
5.0V
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FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
:
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 18: V
OHV
and V
OLP
are measured with respect to ground reference.
Note 19: Input pulses have the following characteristics: f
1 MHz, t
r
3 ns, t
f
3 ns, skew
150 ps.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
:
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
:
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
7
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74AC
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5
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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7
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AC
Q245
74AC
T
Q
2
4
5
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
11
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AC
Q245
74AC
T
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2
4
5
Qui
e
t Seri
es
Oct
a
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B
i
di
rect
ional
T
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anscei
ver
wit
h
3-ST
A
T
E
I
nput
s/
O
u
t
put
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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