2002 Fairchild Semiconductor Corporation
DS500645
www.fairchildsemi.com
September 2001
Revised February 2002
7
4
AL
VC1683
5 Low
V
o
l
t
a
g
e 18-
Bit
Uni
ver
sal
Bus Dr
iver
wi
th
3.6
V
T
o
le
rant
I
nputs
and
Output
s
74ALVC16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Ouputs (O
n
) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVC16835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 DIMM module specifications
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(CLK to O
n
)
4.5 ns max for 3.0V to 3.6V V
CC
5.5 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
(OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package
Number
Package Description
74ALVC16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74
A
L
VC16835
Connection Diagram
Pin Descriptions
Truth Table
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don't Care, but not floating
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
Pin Names
Description
OE
Output Enable Input (Active LOW)
LE
Latch Enable Input
CLK
Clock Input
I
1
- I
18
Data Inputs
O
1
- O
18
3-STATE Outputs
NC
No Connect
Inputs
Outputs
OE
LE
CLK
I
n
O
n
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
L
L
L
H
H
L
L
H
X
O
0
(Note 2)
L
L
L
X
O
0
(Note 3)
3
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7
4
AL
VC1683
5
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
(Note 6)
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 5: I
O
Absolute Maximum Rating must be observed, limited to 4.6V.
Note 6: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 5)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
4 mA
1.65
1.2
I
OH
=
-
6 mA
2.3
2.0
I
OH
=
-
12 mA
2.3
1.7
2.7
2.2
3.0
2.4
I
OH
=
-
24 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
4 mA
1.65
0.45
I
OL
=
6 mA
2.3
0.4
I
OL
=
12 mA
2.3
0.7
2.7
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 - 3.6
750
A
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4
74
A
L
VC16835
AC Electrical Characteristics
AC Electrical Characteristics Over Load
(Note 7)
Note 7: This parameter is guaranteed by characterization but not tested.
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
f
CLOCK
Clock Frequency
150
150
150
100
MHz
t
W
Pulse Width LE High
3.3
3.3
3.3
4.0
ns
CLK High or Low
3.3
3.3
3.3
4.0
t
S
Setup Time
Data Before CLK
1.7
2.1
2.2
2.5
ns
Data Before LE
CLK High
1.5
1.6
1.9
CLK Low
1.0
1.1
1.3
t
H
Hold Time
Data After CLK
0.7
0.6
0.6
1.0
ns
Data After LE
CLK High
1.4
1.7
1.4
or Low
f
MAX
Maximum Clock Frequency
150
150
150
100
MHz
t
PHL
, t
PLH
Propagation Delay
I to O
1
3.6
4.2
1.0
4.2
1.5
8.4
ns
LE to O
1.3
4.2
4.9
1.3
5.0
1.5
9.8
CLK to O
1.4
4.5
5.2
1.4
5.5
2
9.2
t
PZL
, t
PZH
Output Enable Time
1.1
4.6
5.6
1.4
5.5
1.5
9.8
ns
t
PLZ
, t
PHZ
Output Disable Time
1.3
3.9
4.3
1.0
4.5
1.5
7.6
ns
Symbol
Parameter
R
L
=
500
, V
CC
=
3.3
0.15V
Units
T
A
=
-
0
C to
+
85
C
T
A
=
-
0
C to
+
65
C
C
L
=
0 pF
C
L
=
50 pF
Min
Max
Min Max
t
PHL
, t
PLH
Propagation Delay Bus to Bus
0.9
2.0
1.0
4.0
ns
t
PHL
, t
PLH
Propagation Delay Clock to Bus
1.5
2.9
1.7
4.5
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
Control
V
I
=
0V or V
CC
3.3
3
pF
Data
V
I
=
0V or V
CC
3.3
6
C
OUT
Output Capacitance
V
I
=
0V or V
CC
3.3
7
pF
C
PD
Power Dissipation Capacitance
Outputs Enabled f
=
10 MHz, C
L
=
0 pF
3.3
31
pF
2.5
26
Outputs Disabled f
=
10 MHz, C
L
=
0 pF
3.3
14
2.5
12
5
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7
4
AL
VC1683
5
I
OUT
- V
OUT
Characteristics
I
OH
versus V
OH
FIGURE 1. Characteristics for Output - Pull Up Driver
I
OL
versus V
OL
FIGURE 2. Characteristics for Output - Pull Down Driver
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6
74
A
L
VC16835
AC Loading and Waveforms
FIGURE 3. AC Test Circuit
TABLE 1.
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
)
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
t
r
=
t
f
2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
t
r
=
t
f
2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
t
r
=
t
f
2.0ns, 10% to 90%
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
/*2
V
CC
/*2
7
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7
4
AL
VC1683
5 Low
V
o
l
t
a
g
e 18-
Bit
Uni
ver
sal
Bus Dr
iver
wi
th
3.6
V
T
o
le
rant
I
nputs
and
Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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