2001 Fairchild Semiconductor Corporation
DS500668
www.fairchildsemi.com
September 2001
Revised October 2001
7
4
AL
VCF162
835
L
o
w
V
o
lt
age 18-Bi
t Uni
versal
B
u
s
Dr
iver
wi
th 3.
6V
T
o
l
e
rant
O
u
t
put
s
and 26
Seri
es R
e
sist
ors i
n
Out
puts
74ALVCF162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V
Tolerant Outputs and 26
Series Resistors in Outputs
General Description
The 74ALVCF162835 low voltage 18-bit universal bus
driver combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVCF162835 is designed with 26
series resistors
in the outputs. This design reduces noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74ALVCF162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVCF162835 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
I
Compatible with PC133 DIMM module specifications
I
1.65V-3.6V V
CC
specifications provided
I
3.6V tolerant outputs
I
26
series resistors in outputs
I
t
PD
(CLK to O
n
)
3.7 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
7.4 ns max for 1.65V to 1.95V V
CC
I
Power-down high impedance outputs
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package
Number
Package Description
74ALVCF162835T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com
2
74AL
VCF162835
Connection Diagram
Pin Descriptions
Truth Table
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don't Care, but not floating
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
Note 1: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 2: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
Pin Names
Description
OE
Output Enable Input (Active LOW)
LE
Latch Enable Input
CLK
Clock Input
I
1
- I
18
Data Inputs
O
1
- O
18
3-STATE Outputs
Inputs
Outputs
OE
LE
CLK
I
n
O
n
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
L
L
L
H
H
L
L
H
X
O
0
(Note 1)
L
L
L
X
O
0
(Note 2)
3
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7
4
AL
VCF162
835
Absolute Maximum Ratings
(Note 3)
Recommended Operating
Conditions
(Note 5)
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 4: I
O
Absolute Maximum Rating must be observed.
Note 5: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 4)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
2 mA
1.65
1.2
I
OH
=
-
4 mA
2.3
1.9
I
OH
=
-
6 mA
2.3
1.7
3.0
2.4
I
OH
=
-
8 mA
2.7
2
I
OH
=
-
12 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
2 mA
1.65
0.45
I
OL
=
4 mA
2.3
0.4
I
OL
=
6 mA
2.3
0.55
3.0
0.55
I
OL
=
8 mA
2.7
0.6
I
OL
=
12 mA
3.0
0.8
I
OH
High Level Output Current
1.65
-
2
mA
2.3
-
6
2.7
-
8
3.0
-
12
I
OL
Low Level Output Current
1.65
2
mA
2.3
6
2.7
8
3.0
12
I
I
Input Leakage Current
0
V
I
3.6V
1.65 - 3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V, V
I
=
V
IH
or V
IL
1.65 - 3.6
10
A
I
OFF
Power Off Leakage Current
0V
(V
I
, V
O
)
3.6V
0
10
mA
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.7 - 3.6
750
A
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4
74AL
VCF162835
AC Electrical Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
250
200
200
100
MHz
t
PHL
, t
PLH
Propagation Delay
1.1
3.6
1.3
4.5
0.8
4.0
1.5
7.2
ns
Bus-to-Bus
t
PHL
, t
PLH
Propagation Delay
1.5
3.7
2.0
4.6
1.5
4.1
2.0
7.4
ns
Clock to Bus
t
PHL
, t
PLH
Propagation Delay
1.1
4.2
1.3
5.2
0.8
4.7
1.5
8.5
ns
LE to Bus
t
PZL
, t
PZH
Output Enable Time
1.1
4.8
1.3
6.4
0.8
5.9
1.5
9.8
ns
t
PLZ
, t
PHZ
Output Disable Time
1.1
4.7
1.3
5.2
0.8
4.7
1.5
7.9
ns
t
S
Setup Time
1.5
1.5
1.5
2.5
ns
t
H
Hold Time
0.7
0.7
0.7
1.0
ns
t
W
Pulse Width
1.5
1.5
1.5
4.0
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
V
I
=
0V or V
CC
3.3
3.5
pF
C
OUT
Output Capacitance
V
I
=
0V or V
CC
3.3
5.5
pF
C
PD
Power Dissipation Capacitance
Outputs Enabled f
=
10 MHz, C
L
=
0 pF
3.3
13
pF
2.5
13
5
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7
4
AL
VCF162
835
I
OUT
- V
OUT
Characteristics
I
OH
versus V
OH
FIGURE 1. Characteristics for Output - Pull Up Drive
I
OL
versus V
OL
FIGURE 2. Characteristics for Output - Pull Down Driver
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6
74AL
VCF162835
AC Loading and Waveforms
FIGURE 3. AC Test Circuit
Table 1: Values for Figure 1
Table 2: Variable Matrix
( Input Charactertistics: f = 1MHz; t
r
=t
f
=2ns; Z
0
= 50
)
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
7
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7
4
AL
VCF162
835
L
o
w
V
o
lt
age 18-Bi
t Uni
versal
B
u
s
Dr
iver
wi
th 3.
6V
T
o
l
e
rant
O
u
t
put
s
and 26
Seri
es R
e
sist
ors i
n
Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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