2002 Fairchild Semiconductor Corporation
DS500648
www.fairchildsemi.com
September 2001
Revised February 2002
7
4
AL
VCH245 Low
V
o
l
t
age Bidi
rec
t
i
onal T
r
a
n
sceiv
e
r w
i
th Bushol
d
74ALVCH245
Low Voltage Bidirectional Transceiver with Bushold
General Description
The ALVCH245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The T/R input determines the direction
of data flow. The OE input disables both the A and B Ports
by placing them in a high impedance state. The ALVCH245
data inputs include active bushold circuitry, eliminating the
need for external pull-up resistors to hold unused or float-
ing data inputs at a valid logic level.
The 74ALVCH245 is designed for low voltage (1.65V to
3.6V) V
CC
applications.
The 74ALVCH245 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
t
PD
3.6 ns max for 3.0V to 3.6V V
CC
4.2 ns max for 2.3V to 2.7V V
CC
6 ns max for 1.65V to 1.95V V
CC
s
Uses patented Quiet Series noise/EMI reduction
circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Quiet Series
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ALVCH245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ALVCH245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
T/R
Transmit/Receive Input
A
0
A
7
Side A Bushold Inputs or 3-STATE Outputs
B
0
B
7
Side B Bushold Inputs or 3-STATE Outputs
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2
74AL
V
CH245
Connection Diagram
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Logic Diagram
Inputs
Outputs
OE
T/R
L
L
Bus B
0
B
7
Data to Bus A
0
A
7
L
H
Bus A
0
A
7
Data to Bus B
0
B
7
H
X
HIGH Z State on A
0
A
7
, B
0
B
7
3
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7
4
AL
VCH245
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 2: I
O
Absolute Maximum Rating must be observed, limited to 4.6V.
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 2)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
4 mA
1.65
1.2
I
OH
=
-
6 mA
2.3
2.0
I
OH
=
-
12 mA
2.3
1.7
2.7
2.2
3.0
2.4
I
OH
=
-
24 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
4 mA
1.65
0.45
I
OL
=
6 mA
2.3
0.4
I
OL
=
12 mA
2.3
0.7
2.7
0.4
I
OL
=
24 mA
3.0
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
I(HOLD)
Bushold Input Minimum
V
IN
=
0.58V
1.65
25
A
Drive Hold Current
V
IN
=
1.07V
1.65
-
25
V
IN
=
0.7V
2.3
45
V
IN
=
1.7V
2.3
-
45
V
IN
=
0.8V
3.0
75
V
IN
=
2.0V
3.0
-
75
0
<
V
O
3.6V
3.6
500
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
10
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 - 3.6
750
A
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4
74AL
V
CH245
AC Electrical Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
t
PHL
, t
PLH
Propagation Delay
1.3
3.6
4.2
1.0
3.7
1.5
6.0
ns
t
PZL
, t
PZH
Output Enable Time
1.6
5.5
6.3
2.0
6.0
2.9
8.6
ns
t
PLZ
, t
PHZ
Output Disable Time
1.7
5.5
5.3
0.8
4.8
1.5
8.0
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
Control
V
I
=
0V or V
CC
3.3
4.5
pF
C
I/O
Input/Output Capacitance
A or B Ports
V
I
=
0V or V
CC
3.3
12
pF
C
PD
Power Dissipation Capacitance
Outputs Enabled f
=
10 MHz, C
L
=
0 pF
3.3
31
pF
2.5
28
1.8
25
Outputs Disabled f
=
10 MHz, C
L
=
50 pF
3.3
0
2.5
0
1.8
0
5
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4
AL
VCH245
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
TABLE 1. Values for Figure 1
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
)
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
x
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
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6
74AL
V
CH245
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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7
4
AL
VCH245 Low
V
o
l
t
age Bidi
rec
t
i
onal T
r
a
n
sceiv
e
r w
i
th Bushol
d
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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