2001 Fairchild Semiconductor Corporation
DS500660
www.fairchildsemi.com
September 2001
Revised October 2001
7
4
AL
VCR16260
1
Low V
o
l
t
a
g
e
18-
Bit
Uni
ver
sal Bus
T
r
anscei
vers
wit
h
3.6V T
o
ler
a
nt Inp
u
ts and O
u
t
puts
and 26
Ser
i
es
Resi
stor
s i
n
the
Output
s
74ALVCR162601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
and 26
Series Resistors in the Outputs
General Description
The 74ALVCR162601, 18-bit universal bus transceiver,
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74ALVCR162601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVCR162601 is also designed with 26
series
resistors on both the A and B Port outputs. This design
reduces line noise in applications such as memory address
drivers, clock drivers, and bus transceivers/transmitters.
Features
I
1.653.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
26
series resistors on both the A and B Port outputs.
I
t
PD
(A to B, B to A)
4.3 ns max for 3.0V to 3.6V V
CC
5.1 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
I
Power-down HIGH impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package
Number
Package Description
74ALVCR162601T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com
2
74
A
L
VCR162601
Connection Diagram
Pin Descriptions
Function Table
(Note 2)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
HIGH Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 3: Output level before the indicated steady-state input conditions
were established
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Logic Diagram
Pin Names
Description
OEAB, OEBA
Output Enable Inputs (Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A
1
A
18
Side A Inputs or 3-STATE Outputs
B
1
B
18
Side B Inputs or 3-STATE Outputs
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
A
n
B
n
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B
0
(Note 3)
H
L
L
X
X
B
0
(Note 3)
L
L
L
L
L
L
L
L
H
H
L
L
L
L
X
B
0
(Note 3)
L
L
L
H
X
B
0
(Note 4)
3
www.fairchildsemi.com
7
4
AL
VCR16260
1
Absolute Maximum Ratings
(Note 5)
Recommended Operating
Conditions
(Note 7)
Note 5: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 6: I
O
Absolute Maximum Rating must be observed.
Note 7: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 6)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
2 mA
1.65
1.2
I
OH
=
-
4 mA
2.3
1.9
I
OH
=
-
6 mA
2.3
1.7
3.0
2.4
I
OH
=
-
8 mA
2.7
2
I
OH
=
-
12 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
2 mA
1.65
0.45
I
OL
=
4 mA
2.3
0.4
I
OL
=
6 mA
2.3
0.55
3.0
0.55
I
OL
=
8 mA
2.7
0.6
I
OL
=
12 mA
3.0
0.8
I
OH
High Level Output Current
1.65
-
2
mA
2.3
-
6
2.7
-
8
3.0
-
12
I
OL
Low Level Output Current
1.65
2
mA
2.3
6
2.7
8
3.0
12
I
I
Input Leakage Current
0
V
I
3.6V
1.65 - 3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V, V
I
=
V
IH
or V
IL
1.65 - 3.6
10
A
I
OFF
Power Off Leakage Current
0V
(V
I
, V
O
)
3.6V
0
10
mA
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.7 - 3.6
750
A
www.fairchildsemi.com
4
74
A
L
VCR162601
AC Electrical Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
250
200
200
125
MHz
t
PHL
, t
PLH
Propagation Delay
1.1
4.3
1.3
5.1
0.8
4.6
1.5
9.2
ns
A to B or B to A
t
PHL
, t
PLH
Propagation Delay
1.1
4.9
1.3
6.0
0.8
5.5
1.5
9.8
ns
Clock to A or B
t
PHL
, t
PLH
Propagation Delay
1.1
4.9
1.3
6.3
0.8
5.8
1.5
9.8
ns
LEBA or LEAB to A or B
t
PZL
, t
PZH
Output Enable Time
1.1
4.8
1.3
6.4
0.8
5.9
1.5
9.8
ns
OEBA or OEAB to A or B
t
PLZ
, t
PHZ
Output Disable Time
1.1
4.8
1.3
5.4
0.8
4.9
1.5
8.8
ns
OEBA or OEAB to A or B
t
S
Setup Time
1.5
1.5
1.5
2.5
ns
t
H
Hold Time
1.0
1.0
1.0
1.0
ns
t
W
Pulse Width
1.5
1.5
1.5
4.0
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
V
I
=
0V or V
CC
3.3
6
pF
C
OUT
Output Capacitance
V
I
=
0V or V
CC
3.3
7
pF
C
PD
Power Dissipation Capacitance
Outputs Enabled f
=
10 MHz, C
L
=
0 pF
3.3
20
pF
2.5
20
5
www.fairchildsemi.com
7
4
AL
VCR16260
1
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
Table 1: Values for Figure 1
Table 2: Variable Matrix
( Input Charactertistics: f = 1MHz; t
r
=t
f
=2ns; Z
0
= 50
)
FIGURE 2. Waveform for Inverting
and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable
and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable
and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width
and t
rec
Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
www.fairchildsemi.com
6
74AL
VCR162601 Low
V
o
l
t
age
18-
Bit
Uni
versa
l Bus
T
r
anscei
vers wit
h
3.
6V T
o
l
e
ra
nt Input
s and
Out
puts and 26
Ser
i
es
Resis
t
ors
i
n
t
he
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP