October 1987
Revised January 1999
MM74C86
Q
u
ad 2-
Inp
u
t
EXC
LUSI
VE-OR Gat
e
1999 Fairchild Semiconductor Corporation
DS005887.prf
www.fairchildsemi.com
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digi-
tal integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
CC
and GND.
Features
s
Wide supply voltage range:
3.0V to 15V
s
Guaranteed noise margin:
1.0V
s
High noise immunity:
0.45 V
CC
(typ.)
s
Low power:
TTL compatibility:
Fan out of 2 driving 74L
s
Low power consumption:
10 nW/package (typ.)
s
The MM74C86 follows the MM74LS86 Pinout
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
H
=
HIGH Level
L
=
LOW Level
Order Number
Package Number
Package Description
MM74C86M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
MM74C86N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Inputs
Output
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
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2
MM
74C86
Absolute Maximum Ratings
(Note 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/max limits apply across temperature range unless otherwise noted
AC Electrical Characteristics
(Note 2)
T
A
=
25
C, C
L
=
50 pF, unless otherwise specified
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note--
AN-90.
Voltage at any Pin (Note 1)
-
0.3V to V
CC
+
0.3V
Operating Temperature Range
-
40
C to
+
85
C
Storage Temperature Range
-
65
C to
+
150
C
Power Dissipation (P
D
)
Dual-In-Line Package
700 mW
Small Outline
500 mW
Operating Range (V
CC
)
3.0V to 15V
Absolute Maximum (V
CC
)
18V
Lead Temperature
(Soldering, 10 seconds)
260
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5.0V
3.5
V
V
CC
=
10V
8.0
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
5.0V
1.5
V
V
CC
=
10V
2.0
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
5.0V, I
O
=
-
10
A
4.5
V
V
CC
=
10V, I
O
=
-
10
A
9.0
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
5.0V, I
O
=
+
10
A
0.5
V
V
CC
=
10V, I
O
=
+
10
A
1.0
V
I
IN(1)
Logical "1" Input Current
V
CC
=
15V, V
IN
=
15V
0.005
1.0
A
I
IN(0)
Logical "0" Input Current
V
CC
=
15V, V
IN
=
0V
-
1.0
-
0.005
A
I
CC
Supply Current
V
CC
=
15V
0.01
15
A
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
1.5
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
4.75V, I
O
=
-
360
A
2.4
V
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
4.75V, I
O
=
360
A
0.4
V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
Output Source Current
V
CC
=
5.0V, V
OUT
=
0V
-
1.75
-
3.3
mA
(P-Channel)
T
A
=
25
C
I
SOURCE
Output Source Current
V
CC
=
10V, V
OUT
=
0V
-
8.0
-
15
mA
(P-Channel)
T
A
=
25
C
I
SINK
Output Sink Current
V
CC
=
5.0V, V
OUT
=
V
CC
1.75
3.6
mA
(N-Channel)
T
A
=
25
C
I
SINK
Output Sink Current
V
CC
=
10V, V
OUT
=
V
CC
8.0
16
mA
(N-Channel)
T
A
=
25
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Time to Logical
V
CC
=
5.0V
110
185
ns
"1" or "0"
V
CC
=
10V
50
90
ns
C
IN
Input Capacitance
(Note 3)
5.0
pF
C
PD
Power Dissipation Capacitance
Per Gate (Note 4)
20
pF
3
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MM74C86
Typical Performance Characteristics
Propagation Delay Time vs
Load Capacitance
Test Circuits and Waveforms
Delays Measured with Input t
r,
t
f
=
20 ns
FIGURE 1. AC Test Circuit
FIGURE 2. Switching Time Waveforms
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4
MM
74C86
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
Package Number M14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74C86
Q
u
ad 2-
Inp
u
t
EXC
LUSI
VE-OR Gat
e
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
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