October 1987
Revised January 1999
MM74C911 4-Di
git
E
x
pandab
le
Segment Dis
p
la
y Contr
o
ll
er
1999 Fairchild Semiconductor Corporation
DS005915.prf
www.fairchildsemi.com
MM74C911
4-Digit Expandable Segment Display Controller
General Description
The MM74C911 display controller is an interface element
with memory that drives a 4-digit, 8-segment LED display.
The MM74C911 allows individual control of any segment in
the 4-digit display. The number of segments per digit can
be expanded without any external components. For exam-
ple, two MM74C911's can be cascaded to drive a 16-seg-
ment alpha-numeric display.
The display controllers receive data information through 8
data lines a, b...DP, and digit information through 2
address inputs K1 and K2. The input data is written into the
register selected by the address information when CHIP
ENABLE, CE, and WRITE ENABLE, WE, are LOW and is
latched when either CE or WE return HIGH. Data hold time
is not required.
A self-contained internal oscillator sequentially presents
the stored data to high drive (100 mA typ.) 3-STATE output
drivers which directly drive the LED display. The drivers are
active when the control pin labeled SEGMENT OUTPUT
ENABLE, SOE, is LOW and go into 3-STATE when SOE is
HIGH. This feature allows for duty cycle brightness control,
or for disabling the output drive for power conservation.
The digit outputs directly drive the base of the digit transis-
tor when the control pin labeled DIGIT INPUT OUTPUT,
DIO, is LOW. When DIO is HIGH, the digit lines turn into
inputs and the internal scanning multiplexer is disabled.
When any digit line is forced HIGH by an external device,
usually another MM74C911, the data information for that
digit is presented to the output. In this manner, 16-segment
alpha-numeric displays, 24- or 32-segment displays, or an
array of discrete LED's can be controlled by the simple cas-
cading of expandable segment display controllers. All
inputs except digit inputs are TTL compatible and do not
clamp input voltages above V
CC
.
Features
s
Direct segment drive (100 mA typ.) 3-STATE
s
4 registers addressed like RAM
s
Internal oscillator and scanning circuit
s
Direct base drive to digit transistor
s
Segment expandability without external components
s
TTL compatible inputs
s
Power saver mode--5
W (typ.)
Ordering Code:
Connection Diagram
Pin Assignments for DIP
Top View
Order Number
Package Number
Package Description
MM74C991N
N28B
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS
-
010, 0.600" Wide
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2
M
M
74C911
Truth Tables
Input Control
Output Control
R
=
Refresh (digit lines sequentially pulsed)
X
=
Don't Care
Functional Description
The MM74C911 display controller is manufactured on stan-
dard metal gate CMOS technology. A single 5V 74 series
TTL supply can be used for power and should be bypassed
at the V
CC
pin to suppress current transients.
The digit outputs directly drive the base of a grounded
emitter digit transistor without the need of a Darlington con-
figuration. If an MM74C911 is driving a digit transistor and
also supplying digit information to a cascaded MM74C911,
base resistors are needed in the digit transistors to provide
an adequate high level to the digit inputs of the cascaded
MM74C911.
As seen in the Block Diagram, these display controllers
contain four 8-bit registers; any one may be randomly writ-
ten into. In normal operation, the internal multiplexer scans
the registers and refreshes the display. In cascaded opera-
tion, 1 MM74C911 serves as a master refresh device and
cascaded MM74C911's are slaved to it through digit lines
operating as inputs.
The MM74C911 appears to a microprocessor as memory
and to the user as a self-scan display. Since every seg-
ment is under microprocessor control, great versatility is
obtained.
Low power standby operation occurs with both SOE and
DIO inputs HIGH. This condition forces the MM74C911 to a
quiescent state typically drawing less than 1
A of supply
current with a standby supply voltage as low as 3V.
Logic Diagram
Digit
CE
Address
WE
Operation
K2
K1
0
0
0
0
Write Digit 1
0
0
0
1
Latch Digit 1
0
0
1
0
Write Digit 2
0
0
1
1
Latch Digit 2
0
1
0
0
Write Digit 3
0
1
0
1
Latch Digit 3
0
1
1
0
Write Digit 4
0
1
1
1
Latch Digit 4
1
X
X
X
Disable Writing
DIO
SOE
Digit Lines
Operation
D4 D3 D2 D1
0
0
R
R
R
R
Refresh Display
0
1
R
R
R
R
Disable Segment Outputs
1
0
0
0
0
0
Digits Are Now Inputs
1
0
0
0
0
1
Display Digit 1
1
0
0
0
1
0
Display Digit 2
1
0
0
1
0
0
Display Digit 3
1
0
1
0
0
0
Display Digit 4
1
1
0
0
0
0
Power Saver Mode
3
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MM74C911
Absolute Maximum Ratings
(Note 1)
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Range",
they are not meant to imply that the device should be operated at these lim-
its. The table of "Electrical Characteristics" provides conditions for actual
device operation.
Note 2: All voltage reference to ground.
DC Electrical Characteristics
Min/Max limits apply at
-
40
C
T
J
+
85
C, unless otherwise noted
Note 3:
JA
measured in free-air with device soldered into printed circuit board.
Voltage at Any Pin
except Inputs
-
0.3V to V
CC
+
0.3V
Voltage at Any Input
except Digits
-
0.3V to
+
15V
Operating Temperature
Range, (T
A
)
-
40
C to
+
85
C
Storage Temperature Range
-
65
C to
+
150
C
Power Dissipation (P
D
)
Refer to P
D(MAX)
vs T
A
Graph
Operating V
CC
Range
3V to 6V
Absolute Maximum V
CC
6.5V
Lead Temperature
(Soldering, 10 seconds)
260
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5V
3.0
V
V
IN(0)
Logical "0" Input Voltage
1.5
V
I
IN(1)
Logical "1" Input Current
V
CC
=
5V, V
IN
=
15V
0.005
1.0
A
I
IN(0)
Logical "0" Input Current
V
CC
=
5V, V
IN
=
0V
-
1.0
-
0.005
A
I
CC
Supply Current (Normal)
V
CC
=
5V, Outputs Open
0.50
2.5
mA
I
CC
Supply Current (Power Saver)
V
CC
=
5V, SOE, DIO
=
"1",
1
600
A
D1, D2, D3, D4
=
"0"
I
OUT
3-STATE Output Current
V
O
=
5V
0.03
10
A
V
O
=
0V
-
10
-
0.03
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
2
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
OUTPUT DRIVE
I
SH
HIGH Level Segment Current
V
CC
=
5V, V
O
=
3.4V
T
J
=
25
C
-
60
-
100
mA
T
J
=
100
C
-
40
-
60
mA
I
DH
HIGH Level Digit Current
V
CC
=
5V, V
O
=
3V
T
J
=
25
C
-
10
-
20
mA
T
J
=
100
C
-
7
-
10
mA
V
CC
=
5V, V
O
=
1V
T
J
=
25
C
-
15
-
40
mA
T
J
=
100
C
-
10
-
15
mA
V
OUT(1)
Logical "1" Output Voltage,
V
CC
=
5V, I
O
=
-
360
A
4.6
V
Any Digit
V
OUT(0)
Logical "0" Output Voltage,
V
CC
=
5V, I
O
=
360
A
0.4
V
Any Output
JA
Thermal Resistance
(Note 3)
100
C/W
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4
M
M
74C911
AC Electrical Characteristics
(Note 4)
V
CC
=
5V, t
r
=
t
f
=
20 ns, C
L
=
50 pF
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: Capacitance guaranteed by periodic testing.
Switching Time Waveforms
Write Data Waveforms
3-STATE Waveforms
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
CW
Chip Enable to Write Enable Set-Up Time
T
J
=
25
C
35
15
ns
T
J
=
125
C
50
20
ns
t
AW
Address to Write Enable Set-Up Time
T
J
=
25
C
35
15
ns
T
J
=
125
C
50
20
ns
t
WW
Write Enable Width
T
J
=
25
C
400
225
ns
T
J
=
125
C
450
250
ns
t
DW
Data to Write Enable Set-Up Time
T
J
=
25
C
390
225
ns
T
J
=
125
C
430
250
ns
t
WD
Write Enable to Data Hold Time
T
J
=
25
C
0
-
10
ns
T
J
=
125
C
0
-
15
ns
t
WA
Write Enable to Address Hold Time
T
J
=
25
C
0
-
10
ns
T
J
=
125
C
0
-
15
ns
t
WC
Write Enable to Chip Enable Hold Time
T
J
=
25
C
55
30
ns
T
J
=
125
C
75
40
ns
t
1H
, t
0H
Logical "1", Logical "0" Levels into 3-STATE
R
L
=
10k, C
L
=
10 pF
T
J
=
25
C
275
500
ns
T
J
=
125
C
325
600
ns
t
H1
, t
H0
3-STATE to Logical "1" or
R
L
=
10k, C
L
=
10 pF
Logical "0" Levels
T
J
=
25
C
325
600
ns
T
J
=
125
C
375
700
ns
t
D1
, t
D0
Propagation Delay from Digit Input to
T
J
=
25
C
500
1000
ns
Segment Output
T
J
=
125
C
700
1400
ns
t
IB
Interdigit Blanking Time
T
J
=
25
C
5
10
s
T
J
=
125
C
10
20
s
f
MUX
Multiplex Scan Frequency
T
J
=
25
C
525
Hz
T
J
=
125
C
375
Hz
C
IN
Input Capacitance
(Note 5)
5
7.5
pF
C
OUT
3-STATE Output Capacitance
(Note 5)
30
50
pF
5
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MM74C911
Switching Time Waveforms
(Continued)
Multiplexing Output Waveforms
Read Data Waveforms
Note A: All other digit lines are at a low level. DIO at a HIGH level.
Typical Performance Characteristics
Segment outputs if shorted to ground will exceed maximum
power dissipation of the device.
V
CE
is the saturation voltage of the digit drive transistor.
Power Dissipation vs
Temperature for
Plastic Packages
Applications
Segment Output Structure
Digit Output Structure
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6
M
M
74C911
Input Protection
Segment Expansion
Typical Application
*Base resistors may be necessary to limit base current.
7
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MM74C911
4-Digit, 16-Segment Alpha-Numeric Display
Segment
Identification
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM
74
C
9
11 4-
Digi
t
Expandab
l
e
Segm
ent
Di
spl
a
y
Cont
r
o
l
l
er
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide
Package Number N28B
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