October 1987
Revised January 1999
MM74C925
MM74C926
MM74C927
MM74C928 4
-
Di
git
Count
er
s wi
th
M
u
l
t
i
pl
e
x
ed
7-Se
gm
ent
Out
put
Dri
ver
s
1999 Fairchild Semiconductor Corporation
DS005919.prf
www.fairchildsemi.com
MM74C925 MM74C926 MM74C927 MM74C928
4-Digit Counters with Multiplexed
7-Segment Output Drivers
General Description
The MM74C925, MM74C926, MM74C927 and MM74C928
CMOS counters consist of a 4-digit counter, an internal out-
put latch, NPN output sourcing drivers for a 7-segment dis-
play, and an internal multiplexing circuitry with four
multiplexing outputs. The multiplexing circuit has its own
free-running oscillator, and requires no external clock. The
counters advance on negative edge of clock. A HIGH sig-
nal on the Reset input will reset the counter to zero, and
reset the carry-out LOW. A LOW signal on the Latch
Enable input will latch the number in the counters into the
internal output latches. A HIGH signal on Display Select
input will select the number in the counter to be displayed;
a LOW level signal on the Display Select will select the
number in the output latch to be displayed.
The MM74C925 is a 4-decade counter and has Latch
Enable, Clock and Reset inputs.
The MM74C926 is like the MM74C925 except that it has a
display select and a carry-out used for cascading counters.
The carry-out signal goes HIGH at 6000, goes back LOW
at 0000.
The MM74C927 is like the MM74C926 except the second
most significant digit divides by 6 rather than 10. Thus, if
the clock input frequency is 10 Hz, the display would read
tenths of seconds and minutes (i.e., 9:59.9).
The MM74C928 is like the MM74C926 except the most sig-
nificant digit divides by 2 rather than 10 and the carry-out is
an overflow indicator which is HIGH at 2000, and it goes
back LOW only when the counter is reset. Thus, this is a
3-digit counter.
Features
s
Wide supply voltage range:
3V to 6V
s
Guaranteed noise margin:
1V
s
High noise immunity:
0.45 V
CC
(typ.)
s
High segment sourcing current:
40 mA
@ V
CC
-
1.6V, V
CC
=
5V
s
Internal multiplexing circuitry
Design Considerations
Segment resistors are desirable to minimize power dissipa-
tion and chip heating. The DS75492 serves as a good digit
driver when it is desired to drive bright displays. When
using this driver with a 5V supply at room temperature, the
display can be driven without segment resistors to full illu-
mination. The user must use caution in this mode however,
to prevent overheating of the device by using too high a
supply voltage or by operating at high ambient tempera-
tures.
The input protection circuitry consists of a series resistor,
and a diode to ground. Thus input signals exceeding V
CC
will not be clamped. This input signal should not be allowed
to exceed 15V.
Ordering Code:
Order Number
Package Number
Package Description
MM74C925N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C926N
N18A
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C927N
N18A
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74C928N
N18A
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
MM74C925
MM
7
4
C926
MM
74
C
9
2
7
M
M
74C928
Connection Diagrams
Pin Assignments for DIP
Top View
MM74C925
Top View
MM74C926, MM74C927, MM74C928
Functional Description
Reset
-- Asynchronous, active high
Display Select -- High, displays output of counter
Low, displays output of latch
Latch Enable -- High, flow through condition
Low, latch condition
Clock --Negative
edge
sensitive
Segment Output -- Current sourcing with 40 mA @V
OUT
=
V
CC
-
1.6V (typ.) Also, sink capability
=
2
LTTL loads
Digit Output -- Current sourcing with 1 mA @V
OUT
=
1.75V. Also, sink capability
=
2 LTTL loads
Carry-Out
-- 2 LTTL loads. See carry-out waveforms.
Logic Diagrams
MM74C925
3
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MM74C925
MM74C926
MM74C927
MM74C928
Logic Diagrams
(Continued)
MM74C926
MM74C927
MM74C928
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4
MM74C925
MM
7
4
C926
MM
74
C
9
2
7
M
M
74C928
Absolute Maximum Ratings
(Note 1)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/Max limits apply at
-
40
C
t
j
+
85
C, unless otherwise noted
Note 2:
jA
measured in free-air with device soldered into printed circuit board.
Voltage at Any Output Pin
GND
-
0.3V to V
CC
+
0.3V
Voltage at Any Input Pin
GND
-
0.3V to
+
15V
Operating Temperature
Range (T
A
)
-
40
C to
+
85
C
Storage Temperature
Range
-
65
C to
+
150
C
Power Dissipation (P
D
)
Refer to P
D(MAX)
vs T
A
Graph
Operating V
CC
Range
3V to 6V
V
CC
6.5V
Lead Temperature
(Soldering, 10 seconds)
260
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
IN(1)
Logical "1" Input Voltage
V
CC
=
5V
3.5
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
5V
1.5
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
5V, I
O
=
-
10
A
(Carry-Out and Digit Output
4.5
V
Only)
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
5V, I
O
=
10
A
0.5
V
I
IN(1)
Logical "1" Input Current
V
CC
=
5V, V
IN
=
15V
0.005
1
A
I
IN(0)
Logical "0" Input Current
V
CC
=
5V, V
IN
=
0V
-
1
-
0.005
A
I
CC
Supply Current
V
CC
=
5V, Outputs Open Circuit,
20
1000
A
V
IN
=
0V or 5V
CMOS/LPTTL INTERFACE
V
IN(1)
Logical "1" Input Voltage
V
CC
=
4.75V
V
CC
-
2
V
V
IN(0)
Logical "0" Input Voltage
V
CC
=
4.75V
0.8
V
V
OUT(1)
Logical "1" Output Voltage
V
CC
=
4.75V,
(Carry-Out and Digit
I
O
=
-
360
A
2.4
V
Output Only)
V
OUT(0)
Logical "0" Output Voltage
V
CC
=
4.75V, I
O
=
360
A
0.4
V
OUTPUT DRIVE
V
OUT
Output Voltage (Segment
I
OUT
=
-
65 mA, V
CC
=
5V, T
j
=
25
C
V
CC
-
2
V
CC
-
1.3
V
Sourcing Output)
I
OUT
=
-
40 mA, V
CC
=
5V
T
j
=
100
C
V
CC
-
1.6
V
CC
-
1.2
V
T
j
=
150
C
V
CC
-
2
V
CC
-
1.4
V
R
ON
Output Resistance (Segment
I
OUT
=
-
65 mA, V
CC
=
5V, T
j
=
25
C
20
32
Sourcing Output)
I
OUT
=
-
40 mA, V
CC
=
5V
T
j
=
100
C
30
40
T
j
=
150
C
35
50
Output Resistance (Segment
0.6
0.8
%/
C
Output) Temperature Coefficient
I
SOURCE
Output Source Current
V
CC
=
4.75V, V
OUT
=
1.75V, T
j
=
150
C
-
1
-
2
mA
(Digit Output)
I
SOURCE
Output Source Current
V
CC
=
5V, V
OUT
=
0V, T
j
=
25
C
-
1.75
-
3.3
mA
(Carry-Out)
I
SINK
Output Sink Current
V
CC
=
5V, V
OUT
=
V
CC
, T
j
=
25
C
1.75
3.6
mA
(All Outputs)
jA
Thermal Resistance
MM74C925:
(Note 2)
75
100
C/W
MM74C926, MM74C927, MM74C928
70
90
C/W
5
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MM74C925
MM74C926
MM74C927
MM74C928
AC Electrical Characteristics
(Note 3)
T
A
=
25
C, C
L
=
50 pF, unless otherwise noted
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Typical Performance Characteristics
Typical Segment Current
vs Output Voltage
Note: V
D
=
Voltage across digit driver
Maximum Power Dissipation
vs Ambient Temperature
Typical Average Segment
Current vs Segment
Resistor Value
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f
MAX
Maximum Clock Frequency
V
CC
=
5V,
T
j
=
25
C
2
4
MHz
Square Wave Clock T
j
=
100
C
1.5
3
MHz
t
r
, t
f
Maximum Clock Rise or Fall Time
V
CC
=
5V
15
s
t
WR
Reset Pulse Width
V
CC
=
5V
T
j
=
25
C
250
100
ns
T
j
=
100
C
320
125
ns
t
WLE
Latch Enable Pulse Width
V
CC
=
5V
T
j
=
25
C
250
100
ns
T
j
=
100
C
320
125
ns
t
SET(CK, LE)
Clock to Latch Enable Set-Up Time
V
CC
=
5V
T
j
=
25
C
2500
1250
ns
T
j
=
100
C
3200
1600
ns
t
LR
Latch Enable to Reset Wait Time
V
CC
=
5V
T
j
=
25
C
0
-
100
ns
T
j
=
100
C
0
-
100
ns
t
SET(R, LE)
Reset to Latch Enable Set-Up Time
V
CC
=
5V
T
j
=
25
C
320
160
ns
T
j
=
100
C
400
200
ns
f
MUX
Multiplexing Output Frequency
V
CC
=
5V
1000
Hz
C
IN
Input Capacitance
Any Input (Note 4)
5
pF
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6
MM74C925
MM
7
4
C926
MM
74
C
9
2
7
M
M
74C928
Typical Performance Characteristics
(Continued)
Segment Output Driver
Input Protection
Common Cathode LED Display
Segment Identification
7
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MM74C925
MM74C926
MM74C927
MM74C928
Switching Time Waveforms
Input Waveforms
Multiplexing Output Waveforms
T
=
1/f
MUX
Carry-Out Waveforms
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8
MM74C925
MM
7
4
C926
MM
74
C
9
2
7
M
M
74C928
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74C925
MM74C926
MM74C927
MM74C928 4
-
Di
git
Count
er
s wi
th
M
u
l
t
i
pl
e
x
ed
7-Se
gm
ent
Out
put
Dri
ver
s
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N18A
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