1999 Fairchild Semiconductor Corporation
DS011685
www.fairchildsemi.com
October 1994
Revised August 1999
7
4F1071 18-Bi
t Undersho
ot/
O
ve
rshoot
Cl
am
p
74F1071
18-Bit Undershoot/Overshoot Clamp
and ESD Protection Device
General Description
The 74F1071 is an 18-bit undershoot/overshoot clamp
which is designed to limit bus voltages and also to protect
more sensitive devices from electrical overstress due to
electrostatic discharge (ESD). The inputs of the device
aggressively clamp voltage excursions nominally at 0.5V
below and 7V above ground.
Features
s
18-bit array structure in 20-pin package
s
FAST
Bipolar voltage clamping action
s
Dual center pin grounds for min inductance
s
Robust design for ESD protection
s
Low input capacitance
s
Optimum voltage clamping for 5V CMOS/TTL
applications
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Note: Simplified Component Representation
FAST
is a registered trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74F1071SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F1071MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F1071MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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2
74F1071
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Voltage ratings may be exceeded if current ratings and junction
temperature and power consumption ratings are not exceeded.
Note 3: ESD Rating for Direct contact discharge using ESD Simulation
Tester. Higher rating may be realized in the actual application.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
65
C to
+
125
C
Junction Temperature under Bias
-
65
C to
+
150
C
Input Voltage (Note 2)
-
0.5V to
+
6V
Input Current (Note 2)
-
200 mA to
+
50 mA
ESD (Note 3)
Human Body Model
(MIL-STD-883D method 3015.7)
10 kV
IEC 801-2
6 kV
Machine Model (EIAJIC-121-1981)
2 kV
DC Latchup Source Current
(JEDEC Method 17)
500 mA
Package Power Dissipation @
+
70
C
SOIC Package
800 mW
Free Air Ambient Temperature
0
C to
+
70
C
Reverse Bias Voltage
0V to 5.25 V
DC
Thermal Resistance (
JA
in Free Air)
SOIC Package
100
C/W
SSOP Package
110
C/W
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
Conditions
Min
Typ
Max
Min
Max
I
IH
Input HIGH Current
1.5
10
50
A
V
IN
=
5.25V; Untested Input @ GND
3
20
100
V
IN
=
5.5V; Untested Input @ GND
V
Z
Reverse Voltage
6.6
6.9
7.2
5.9
7.7
V
I
Z
=
1 mA; Untested Inputs @ GND
7.1
7.5
8.0
I
Z
=
50 mA; Untested Inputs @ GND
V
F
Forward Voltage
-
0.3
-
0.6
-
0.9
-
0.3
-
0.9
V
I
F
=
-
18 mA; Untested Inputs @ 5V
-
0.5
-
1.1
-
1.5
-
0.5
-
1.5
I
F
=
-
200 mA; Untested Inputs @ 5V
I
CT
Adjacent Input Crosstalk
3
%
C
IN
Input Capacitance
25
pF
V
BIAS
=
0 V
DC
(small signal @ 1 MHz)
13
V
BIAS
=
5 V
DC
3
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7
4F1071
DC Electrical Characteristics
Typical Forward and Reverse V/I
Characteristics
Typical Reverse Conduction
Characteristics
Typical Forward Conduction
Characteristics
ESD Network
CZ
RZ
Human Body Model
100 pF
1500
IEC 801-2
150 pF
330
Simulated ESD Voltage Clamping Test Circuit
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4
74F1071
DC Electrical Characteristics
(Continued)
Unclamped + 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Clamped + 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Unclamped - 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Clamped - 1 KV ESD Voltage
Waveform (IEC801-2 Network)
Typical Application
74F1071 ESD Protection of ASIC on User Port
5
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7
4F1071
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
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