1999 Fairchild Semiconductor Corporation
DS009474
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F1
14
D
u
al
JK Negat
iv
e Edge-
T
r
i
ggere
d
Fl
ip-
F
lo
p
74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
General Description
The 74F114 contains two high-speed JK flip-flops with
common Clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to the transition time. The J and K inputs
can change when the clock is in either state without affect-
ing the flip-flop, provided that they are in the desired state
during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on S
D
or C
D
prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on S
D
and C
D
force both Q and
Q HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of Clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F114SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F114PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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14
Unit Loading/Fan Out
Truth Table
H (h)
=
HIGH Voltage Level
L (h)
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Clock Transition
Q
0
(Q
0
)
=
Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(one half shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
J
1
, J
2
, K
1
, K
2
Data Inputs
1.0/1.0
20
A/
-
0.6 mA
CP
Clock Pulse Input (Active Falling Edge)
1.0/8.0
20
A/
-
4.8 mA
C
D
Direct Clear Input (Active LOW)
1.0/10.0
20
A/
-
6.0 mA
S
D1
, S
D2
Direct Set Inputs (Active LOW)
1.0/5.0
20
A/
-
3.0 mA
Q
1
, Q
2
, Q
1
, Q
2
Outputs
50/33.3
-
1 mA/20 mA
Inputs
Outputs
S
D
C
D
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
h
h
Q
0
Q
0
H
H
l
h
L
H
H
H
h
l
H
L
H
H
l
l
Q
0
Q
0
3
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
5% V
CC
2.7
I
OH
=
-
1 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output High
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (J
n
, K
n
)
-
3.0
V
IN
=
0.5V (S
Dn
)
-
4.8
V
IN
=
0.5V (CP)
-
6.0
V
IN
=
0.5V (C
Dn
)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CCH
Power Supply Current
12.0
19.0
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
12.0
19.0
mA
Max
V
O
=
LOW
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AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
75
95
70
MHz
t
PLH
Propagation Delay
3.0
5.0
6.5
3.0
7.5
ns
t
PHL
CP to Q
n
or Q
n
3.0
5.5
7.5
3.0
8.5
t
PLH
Propagation Delay
3.0
4.5
6.5
3.0
7.5
ns
t
PHL
C
Dn
or S
Dn
to Q
n
or Q
n
3.0
4.5
6.5
3.0
7.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
4.0
5.0
ns
t
S
(L)
J
n
or K
n
to CP
3.0
3.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
J
n
or K
n
to CP
0
0
t
W
(H)
CP Pulse Width
4.5
5.0
ns
t
W
(L)
HIGH or LOW
4.5
5.0
t
W
(L)
C
Dn
or S
Dn
Pulse Width,
4.5
5.0
ns
LOW
t
REC
Recovery Time
4.0
5.0
ns
S
Dn
, C
Dn
, to CP
5
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7
4F1
14
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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6
74
F1
14
D
u
a
l
JK Negat
ive
Edge-
T
r
i
ggere
d
Fl
ip-
F
lo
p
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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