1999 Fairchild Semiconductor Corporation
DS009486
www.fairchildsemi.com
April 1988
Revised July 1999
7
4F161A
74F163A Synchr
onous
Pr
eset
tabl
e
Bi
nary Count
er
74F161A 74F163A
Synchronous Presettable Binary Counter
General Description
The 74F161A and 74F163A are high-speed synchronous
modulo-16 binary counters. They are synchronously pre-
settable for application in programmable dividers and have
two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multi-stage
counters. The 74F161A has an asynchronous Master-
Reset input that overrides all other inputs and forces the
outputs LOW. The 74F163A has a Synchronous Reset
input that overrides counting and parallel loading and
allows the outputs to be simultaneously reset on the rising
edge of the clock. The 74F161A and 74F163A are high-
speed versions of the 74F161 and 74F163.
Features
s
Synchronous counting and loading
s
High-speed synchronous expansion
s
Typical count frequency of 120 MHz
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
74F161A
74F163A
Order Number
Package Number
Package Description
74F161ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F161ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F163ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F163ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F161A
74F16
3A
Logic Symbols
74F161A
IEEE/IEC
74F161A
74F163A
IEEE/IEC
74F163A
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CEP
Count Enable Parallel Input
1.0/1.0
20
A/
-
0.6 mA
CET
Count Enable Trickle Input
1.0/2.0
20
A/
-
1.2 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
MR (74F161A)
Asynchronous Master Reset Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
SR (74F163A)
Synchronous Reset Input (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
P
0
P
3
Parallel Data Inputs
1.0/1.0
20
A/
-
0.6 mA
PE
Parallel Enable Input (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
Q
0
Q
3
Flip-Flop Outputs
50/33.3
-
1 mA/20 mA
TC
Terminal Count Output
50/33.3
-
1 mA/20 mA
3
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7
4F161A
74F163A
Functional Description
The 74F161A and 74F163A count in modulo-16 binary
sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the 74F161A) occur as a
result of, and synchronous with, the LOW-to-HIGH transi-
tion of the CP input signal. The circuits have four funda-
mental modes of operation, in order of precedence:
asynchronous reset (74F161A), synchronous reset
(74F163A), parallel load, count-up and hold. Five control
inputs--Master Reset (MR, 74F161A), Synchronous Reset
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-
lel (CEP) and Count Enable Trickle (CET)--determine the
mode of operation, as shown in the Mode Select Table. A
LOW signal on MR overrides all other inputs and asynchro-
nously forces all outputs LOW. A LOW signal on SR over-
rides counting and parallel loading and allows all outputs to
go LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (P
n
) inputs to be loaded into the flip-flops on the next
rising edge of CP. With PE and MR ('F161A) or SR
(74F163A) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The 74F161A and 74F163A use D-type edge triggered flip-
flops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided
that the recommended setup and hold times, with respect
to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and the counter is in state 15. To implement synchro-
nous multi-stage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways. Please
refer to the 74F568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, counters or registers.
Logic Equations: Count Enable
=
CEP CET PE
TC
=
Q
0
Q
1
Q
2
Q
3
CET
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note 1: For 74F163A only
State Diagram
Block Diagram
SR
(Note 1)
PE CET
CE
P
Action on the Rising
Clock Edge (
)
L
X
X
X
Reset (Clear)
H
L
X
X
Load (P
n
Q
n
)
H
H
H
H
Count (Increment)
H
H
L
X
No Change (Hold)
H
H
X
L
No Change (Hold)
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4
74F161A
74F16
3A
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
Voltage
5% V
CC
2.7
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (CEP, CP, MR, P
0
P
3
)
-
1.2
mA
Max
V
IN
=
0.5V (CET, PE, SR)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CC
Power Supply Current
37
55
mA
Max
5
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7
4F161A
74F163A
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Count Frequency
100
120
75
90
MHz
t
PLH
Propagation Delay
3.5
5.5
7.5
3.5
9.0
3.5
8.5
ns
t
PHL
CP to Q
n
(PE Input HIGH)
3.5
7.5
10.0
3.5
11.5
3.5
11.0
t
PLH
Propagation Delay
4.0
6.0
8.5
4.0
10.0
4.0
9.5
t
PHL
CP to Q
n
(PE Input LOW)
4.0
6.0
8.5
4.0
10.0
4.0
9.5
t
PLH
Propagation Delay
5.0
10.0
14.0
5.0
16.5
5.0
15.0
ns
t
PHL
CP to TC
5.0
10.0
14.0
5.0
15.5
5.0
15.0
t
PLH
Propagation Delay
2.5
4.5
7.5
2.5
9.0
2.5
8.5
ns
t
PHL
CET to TC
2.5
4.5
7.5
2.5
9.0
2.5
8.5
t
PHL
Propagation Delay
5.5
9.0
12.0
5.5
14.0
5.5
13.0
ns
MR to Q
n
(74F161A)
t
PHL
Propagation Delay
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns
MR to TC (74F161A)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
5.0
5.5
5.0
ns
t
S
(L)
P
n
to CP
5.0
5.5
5.0
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.5
2.0
t
H
(L)
P
n
to CP
2.0
2.5
2.0
t
S
(H)
Setup Time, HIGH or LOW
11.0
13.5
11.5
ns
t
S
(L)
PE or SR to CP
8.5
10.5
9.5
t
H
(H)
Hold Time, HIGH or LOW
2.0
3.6
2.0
t
H
(L)
PE or SR to CP
0
0
0
t
S
(H)
Setup Time, HIGH or LOW
11.0
13.0
11.5
ns
t
S
(L)
CEP or CET to CP
5.0
6.0
5.0
t
H
(H)
Hold Time, HIGH or LOW
0
0
0
t
H
(L)
CEP or CET to CP
0
0
0
t
W
(H)
Clock Pulse Width (Load)
5.0
5.0
5.0
ns
t
W
(L)
HIGH or LOW
5.0
5.0
5.0
t
W
(H)
Clock Pulse Width (Count)
4.0
5.0
4.0
ns
t
W
(L)
HIGH or LOW
6.0
8.0
7.0
t
W
(L)
MR Pulse Width, LOW
5.0
5.0
5.0
ns
(74F161A)
t
REC
Recovery Time
6.0
6.0
6.0
ns
MR to CP (74F161A)
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6
74F161A
74F16
3A
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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7
4F161A
74F163A Synchr
onous
Pr
eset
tabl
e
Bi
nary Count
er
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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