1999 Fairchild Semiconductor Corporation
DS009488
www.fairchildsemi.com
April 1988
Revised July 1999
7
4F169 4-St
age
Sync
hronous Bidi
rect
i
onal Counte
r
74F169
4-Stage Synchronous Bidirectional Counter
General Description
The 74F169 is a fully synchronous 4-stage up/down
counter. The 74F169 is a modulo-16 binary counter. Fea-
tures a preset capability for programmable operation, carry
lookahead for easy cascading and a U/D input to control
the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the LOW-to-
HIGH transition of the clock.
Features
s
Asynchronous counting and loading
s
Built-in lookahead carry capability
s
Presettable for programmable operation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F169SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F169SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F169PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F169
Unit Loading/Fan Out
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P
0
P
3
inputs enters the flip-flops on the
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable
=
CEP CET PE
2. Up: (74F169): TC
=
Q
0
Q
1
Q
2
Q
3
(Up) CET
3. Down: TC
=
Q
0
Q
1
Q
2
Q
3
(Down) CET
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
State Diagram
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CEP
Count Enable Parallel Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
CET
Count Enable Trickle Input (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
P
0
P
3
Parallel Data Inputs
1.0/1.0
20
A/
-
0.6 mA
PE
Parallel Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
U/D
Up-Down Count Control Input
1.0/1.0
20
A/
-
0.6 mA
Q
0
Q
3
Flip-Flop Outputs
50/33.3
-
1 mA/20 mA
TC
Terminal Count Output (Active LOW)
50/33.3
-
1 mA/20 mA
PE
CEP CET U/D
Action on Rising
Clock Edge
L
X
X
X
Load (P
n
Q
n
)
H
L
L
H
Count Up (Increment)
H
L
L
L
Count Down (Decrement)
H
H
X
X
No Change (Hold)
H
X
H
X
No Change (Hold)
3
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7
4F169
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74F169
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
5% V
CC
2.7
I
OH
=
-
1 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (except CET)
-
1.2
V
IN
=
0.5V (CET)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CCL
Power Supply Current
35
52
mA
Max
V
O
=
LOW
5
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7
4F169
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Count Frequency
90
60
70
MHz
t
PLH
Propagation Delay
3.0
6.5
8.5
3.0
12.0
3.0
9.5
ns
t
PHL
CP to Q
n
(PE HIGH or LOW)
4.0
9.0
11.5
4.0
16.0
4.0
13.0
t
PLH
Propagation Delay
5.5
12.0
15.5
5.5
20.0
5.5
17.5
ns
t
PHL
CP to TC
4.0
8.5
12.5
4.0
15.0
4.0
13.0
t
PLH
Propagation Delay
2.5
4.5
6.5
2.5
9.0
2.5
7.0
ns
t
PHL
CET to TC
2.5
8.5
11.0
2.5
12.0
2.5
12.0
t
PLH
Propagation Delay
3.5
8.5
11.5
3.5
16.0
3.5
12.5
ns
t
PHL
U/D to TC
4.0
8.0
12.0
4.0
14.0
4.0
13.0
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
4.0
4.5
4.5
ns
t
S
(L)
P
n
to CP
4.0
4.5
4.5
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
3.5
t
H
(L)
P
n
to CP
3.0
3.5
3.5
t
S
(H)
Setup Time, HIGH or LOW
7.0
8.0
8.0
ns
t
S
(L)
CEP or CET to CP
5.0
8.0
6.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
0
t
H
(L)
CEP or CET to CP
0.5
1.0
0.5
t
S
(H)
Setup Time, HIGH or LOW
8.0
10.0
9.0
ns
t
S
(L)
PE to CP
8.0
10.0
9.0
t
H
(H)
Hold Time, HIGH or LOW
1.0
1.0
1.0
t
H
(L)
PE to CP
0
0
0
t
S
(H)
Setup Time, HIGH or LOW
11.0
14.0
12.5
ns
t
S
(L)
U/D to CP
7.0
12.0
8.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
0
t
H
(L)
U/D to CP
0
0
0
t
W
(H)
CP Pulse Width
4.0
6.0
4.5
ns
t
W
(L)
HIGH or LOW
7.0
9.0
8.0
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6
74F169
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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7
4F169 4-St
age
Sync
hronous Bidi
rect
i
onal Counte
r
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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