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Электронный компонент: 74F244SJ

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1999 Fairchild Semiconductor Corporation
DS009501
www.fairchildsemi.com
April 1988
Revised July 1999
7
4F240

74F241

74F244 O
c
tal

Buf
f
er
s/Li
ne Driv
ers w
i
t
h

3-
ST
A
T
E O
u
tput
s
74F240 74F241 74F244
Octal Buffers/Line Drivers with 3-STATE Outputs
General Description
The 74F240, 74F241 and 74F244 are octal buffers and line
drivers designed to be employed as memory and address
drivers, clock drivers and bus-oriented transmitters/receiv-
ers which provide improved PC and board density.
Features
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs sink 64 mA (48 mA mil)
s
12 mA source current
s
Input clamp diodes limit high-speed termination effects
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
74F240
74F241
74F244
Order Code
Package Number
Package Description
74F240SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F240PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F241SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F241SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F241PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F244SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F244SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F244MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F244PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com
2
74F240
7
4F241
74F244
Logic Symbols
IEEE/IEC
74F240
IEEE/IEC
74F241
IEEE/IEC
74F244
Unit Loading/Fan Out
Note 1: Worst-case 74F240 enabled; 74F241, 74F244 disabled
Truth Tables
74F240
74F241
74F244
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
OE
1
, OE
2
3-STATE Output Enable Input (Active LOW)
1.0/1.667
20
A/
-
1 mA
OE
2
3-STATE Output Enable Input (Active HIGH)
1.0/1.667
20
A/
-
1 mA
I
0
I
7
Inputs (74F240)
1.0/1.667 (Note 1)
20
A/
-
1 mA
I
0
I
7
Inputs (74F241, 74F244)
1.0/2.667 (Note 1)
20
A/
-
1.6 mA
O
0
O
7
, O
0
O
7
Outputs
600/106.6 (80)
-
12 mA/64 mA (48 mA)
OE
1
D
1n
O
1n
OE
2
D
2n
O
2n
H
X
Z
H
X
Z
L
H
L
L
H
L
L
L
H
L
L
H
OE
1
D
1n
O
1n
OE
2
D
2n
O
2n
H
X
Z
L
X
Z
L
H
H
H
H
H
L
L
L
H
L
L
OE
1
D
1n
O
1n
OE
2
D
2n
O
2n
H
X
Z
H
X
Z
L
H
H
L
H
H
L
L
L
L
L
L
3
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7
4F240

74F241

74F244
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.4
V
Min
I
OH
=
-
3 mA
Voltage
10% V
CC
2.0
I
OH
=
-
15 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.55
V
Min
I
OL
=
64 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
1.0
mA
Max
V
IN
=
0.5V (OE
1
, OE
2
, OE
2
, D
n
74F240))
-
1.6
V
IN
=
0.5V (D
n
(74F241, 74F244))
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
100
-
225
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCH
Power Supply Current (74F240)
19
29
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current (74F240)
50
75
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current (74F240)
42
63
mA
Max
V
O
=
HIGH Z
I
CCH
Power Supply Current
40
60
mA
Max
V
O
=
HIGH
(74F241, 74F244)
I
CCL
Power Supply Current
60
90
mA
Max
V
O
=
LOW
(74F241, 74F244)
I
CCZ
Power Supply Current
60
90
mA
Max
V
O
=
HIGH Z
(74F241, 74F244)
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4
74F240
7
4F241
74F244
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
3.0
5.1
7.0
3.0
9.0
3.0
8.0
ns
t
PHL
Data to Output (74F240)
2.0
3.5
4.7
2.0
6.0
2.0
5.7
t
PZH
Output Enable Time (74F240)
2.0
3.5
4.7
2.0
6.5
2.0
5.7
ns
t
PZL
4.0
6.9
9.0
4.0
10.5
4.0
10.0
t
PHZ
Output Disable Time (74F240)
2.0
4.0
5.3
2.0
6.5
2.0
6.3
t
PLZ
2.0
6.0
8.0
2.0
12.5
2.0
9.5
t
PLH
Propagation Delay
2.5
4.0
5.2
2.0
6.5
2.5
6.2
ns
t
PHL
Data to Output (74F241, 74F244)
2.5
4.0
5.2
2.0
7.0
2.5
6.5
t
PZH
Output Enable Time
2.0
4.3
5.7
2.0
7.0
2.0
6.7
ns
t
PZL
(74F241, 74F244)
2.0
5.4
7.0
2.0
8.5
2.0
8.0
t
PHZ
Output Disable Time
2.0
4.5
6.0
2.0
7.0
2.0
7.0
t
PLZ
(74F241, 74F244)
2.0
4.5
6.0
2.0
7.5
2.0
7.0
5
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7
4F240

74F241

74F244
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
6
74F240
7
4F241
74F244
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
7
www.fairchildsemi.com
7
4F240

74F241

74F244 O
c
tal

Buf
f
er
s/Li
ne Driv
ers w
i
t
h

3-
ST
A
T
E O
u
tput
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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