1999 Fairchild Semiconductor Corporation
DS009504
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F251A
8
-
I
nput Mult
ipl
exer wit
h
3
-
ST
A
T
E
Output
s
74F251A
8-Input Multiplexer with 3-STATE Outputs
General Description
The 74F251A is a high-speed 8-input digital multiplexer. It
provides, in one package, the ability to select one bit of
data from up to eight sources. It can be used as a universal
function generator to generate any logic function of four
variables. Both assertion and negation outputs are pro-
vided.
Features
s
Multifunctional capability
s
On-chip select logic decoding
s
Inverting and non-inverting 3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F251ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F251ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F251APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F25
1A
Unit Loading/Fan Out
Functional Description
This device is a logical implementation of a single-pole, 8-
position switch with the switch position controlled by the
state of three Select inputs, S
0
, S
1
, S
2
. Both assertion and
negation outputs are provided. The Output Enable input
(OE) is active LOW. When it is activated, the logic function
provided at the output is:
Z
=
OE (I
0
S
0
S
1
S
2
+
I
1
S
0
S
1
S
2
+
I
2
S
0
S
1
S
2
+
I
3
S
0
S
1
S
2
+
I
4
S
0
S
1
S
2
+
I
5
S
0
S
1
S
2
+
I
6
S
0
S
1
S
2
+
I
7
S
0
S
1
S
2
)
When the Output Enable is HIGH, both outputs are in the
high impedance (High Z) state. This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the 3-STATE devices are
tied together, all but one device must be in the high imped-
ance state to avoid high currents that would exceed the
maximum ratings. The Output Enable signals should be
designed to ensure there is no overlap in the active LOW
portion of the enable voltages.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
S
0
S
2
Select Inputs
1.0/1.0
20
A/
-
0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
I
0
I
7
Multiplexer Inputs
1.0/1.0
20
A/
-
0.6 mA
Z
3-STATE Multiplexer Output
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Z
Complementary 3-STATE Multiplexer Output
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Inputs
Outputs
OE
S
2
S
1
S
0
Z
Z
H
X
X
X
Z
Z
L
L
L
L
I
0
I
0
L
L
L
H
I
1
I
1
L
L
H
L
I
2
I
2
L
L
H
H
I
3
I
3
L
H
L
L
I
4
I
4
L
H
L
H
I
5
I
5
L
H
H
L
I
6
I
6
L
H
H
H
I
7
I
7
3
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7
4F251A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCL
Power Supply Current
15
22
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
16
24
mA
Max
V
O
=
HIGH Z
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4
74F25
1A
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
3.5
6.0
9.0
3.5
11.5
3.5
9.5
ns
t
PHL
S
n
to Z
3.2
5.0
7.5
3.2
8.0
3.2
7.5
t
PLH
Propagation Delay
4.5
7.5
10.5
3.5
14.0
4.5
12.5
ns
t
PHL
S
n
to Z
4.0
6.0
8.5
3.0
10.5
4.0
9.0
t
PLH
Propagation Delay
3.0
5.0
6.5
2.5
8.0
3.0
7.0
ns
t
PHL
I
n
to Z
1.5
2.5
4.0
1.5
6.0
1.5
5.0
t
PLH
Propagation Delay
3.5
5.0
7.0
2.5
9.0
2.5
8.0
ns
t
PHL
I
n
to Z
3.5
5.5
7.0
3.5
9.0
3.5
7.5
t
PZH
Output Enable Time
2.5
4.3
6.0
2.0
7.0
2.5
7.0
ns
t
PZL
OE to Z
2.5
4.3
6.0
2.5
7.5
2.5
6.5
t
PHZ
Output Disable Time
2.5
4.0
5.5
2.5
6.0
2.5
6.0
t
PLZ
OE to Z
1.5
3.0
4.5
1.5
5.0
1.5
4.5
t
PZH
Output Enable Time
3.5
5.0
7.0
3.0
8.5
3.0
7.5
ns
t
PZL
OE to Z
3.5
5.5
7.5
3.5
9.0
3.5
8.0
t
PHZ
Output Disable Time
2.0
3.8
5.5
2.0
5.5
2.0
5.5
t
PLZ
OE to Z
1.5
3.0
4.5
1.5
5.5
1.5
4.5
5
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7
4F251A
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
74F251A 8-I
nput
Mul
t
i
p
lexe
r
wi
th 3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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