1999 Fairchild Semiconductor Corporation
DS009505
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F253 D
u
a
l
4-I
nput Mult
ip
lexer
wi
th 3-ST
A
T
E
Out
puts
74F253
Dual 4-Input Multiplexer with 3-STATE Outputs
General Description
The 74F253 is a dual 4-input multiplexer with 3-STATE out-
puts. It can select two bits of data from four sources using
common select inputs. The output may be individually
switched to a high impedance state with a HIGH on the
respective Output Enable (OE) inputs, allowing the outputs
to interface directly with bus oriented systems.
Features
s
Multifunction capability
s
Non-inverting 3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F253SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F253SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F253PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F253
Unit Loading/Fan Out
Functional Description
This device contains two identical 4-input multiplexers with
3-STATE outputs. They select two bits from four sources
selected by common Select inputs (S
0
, S
1
). The 4-input
multiplexers have individual Output Enable (OE
a
, OE
b
)
inputs which, when HIGH, force the outputs to a high
impedance (High Z) state. This device is the logic imple-
mentation of a 2-pole, 4-position switch, where the position
of the switch is determined by the logic levels supplied to
the two select inputs. The logic equations for the outputs
are shown below:
Z
a
=
OE
a
(I
0a
S
1
S
0
+
I
1a
S
1
S
0
+
I
2a
S
1
S
0
+
I
3a
S
1
S
0
)
Z
b
=
OE
b
(I
0b
S
1
S
0
+
I
1b
S
1
S
0
+
I
2b
S
1
S
0
+
I
3b
S
1
S
0
)
If the outputs of 3-STATE devices are tied together, all but
one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable signals to 3-
STATE devices whose outputs are tied together are
designed so that there is no overlap.
Truth Table
Address inputs S
0
and S
1
are common to both sections.
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
I
0a
I
3a
Side A Data Inputs
1.0/1.0
20
A/
-
0.6 mA
I
0b
I
3b
Side B Data Inputs
1.0/1.0
20
A/
-
0.6 mA
S
0
S
1
Common Select Inputs
1.0/1.0
20
A/
-
0.6 mA
OE
a
Side A Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
OE
b
Side B Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
Z
a
, Z
b
3-STATE Outputs
150/40(33.3)
-
3 mA/24 mA (20 mA)
Select
Data Inputs
Output
Output
Inputs
Enable
S
0
S
1
I
0
I
1
I
2
I
3
OE
Z
X
X
X
X
X
X
H
Z
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
H
L
X
L
X
X
L
L
H
L
X
H
X
X
L
H
L
H
X
X
L
X
L
L
L
H
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
3
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7
4F253
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
-
100
-
225
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
V
CC
I
CCH
Power Supply Current
11.5
16
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
16
23
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
16
23
mA
Max
V
O
=
HIGH Z
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4
74F253
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
4.5
8.5
11.5
3.5
15.0
4.5
13.0
ns
t
PHL
S
n
to Z
n
3.0
6.5
9.0
2.5
11.0
3.0
10.0
t
PLH
Propagation Delay
3.0
5.5
7.0
2.5
9.0
3.0
8.0
ns
t
PHL
I
n
to Z
n
2.5
4.5
6.0
2.5
8.0
2.5
7.0
t
PZH
Output Enable Time
3.0
6.0
8.0
2.5
10.0
3.0
9.0
ns
t
PZL
3.0
6.0
8.0
2.5
10.0
3.0
9.0
t
PHZ
Output Disable Time
2.0
3.7
5.0
2.0
6.5
2.0
6.0
t
PLZ
2.0
4.4
6.0
2.0
8.0
2.0
7.0
5
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7
4F253
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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