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Электронный компонент: 74F258ASC

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1999 Fairchild Semiconductor Corporation
DS009508
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F258A
Quad 2-
Input

Mul
t
i
p
lex
e
r w
i
th 3-
ST
A
T
E O
u
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put
s
74F258A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a common data select input. The four outputs
present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
Features
s
Multiplexer expansion by tying outputs together
s
Inverting 3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F258ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F258ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F258APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F25
8A
Unit Loading/Fan Out
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I
0x
inputs are selected and when Select
is HIGH, the I
1x
inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
Z
n
=
OE (I
1n
S
+
I
0n
S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
S
Common Data Select Input
1.0/1.0
20
A/
-
0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
I
0a
I
0d
Data Inputs from Source 0
1.0/1.0
20
A/
-
0.6 mA
I
1a
I
1d
Data Inputs from Source 1
1.0/1.0
20
A/
-
0.6 mA
Z
a
Z
d
3-STATE Inverting Data Outputs
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Output
Select
Data
Output
Enable
Input
Inputs
OE
S
I
0
I
1
Z
H
X
X
X
Z
L
H
X
L
H
L
H
X
H
L
L
L
L
X
H
L
L
H
X
L
3
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7
4F258A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
V
CC
I
CCH
Power Supply Current
6.2
9.5
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
15.1
23
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
11.3
17
mA
Max
V
O
=
HIGH Z
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4
74F25
8A
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
5
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
2.5
5.3
2.0
7.5
2.0
6.0
ns
t
PHL
I
n
to Z
n
1.0
4.0
1.0
6.0
1.0
5.0
t
PLH
Propagation Delay
3.0
7.5
3.0
9.5
3.0
8.5
ns
t
PHL
S to Z
n
2.5
7.0
2.5
9.0
2.5
8.0
t
PZH
Output Enable Time
2.0
6.0
2.0
8.0
2.0
7.0
ns
t
PZL
2.5
7.0
2.5
9.0
2.5
8.0
t
PHZ
Output Disable Time
2.0
6.0
1.5
7.0
2.0
7.0
t
PLZ
2.0
6.0
2.0
8.5
2.0
7.0
5
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7
4F258A
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
74
F258A Quad
2-I
nput
Mul
t
i
p
lexe
r wi
th
3-
S
T
A
T
E
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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