1999 Fairchild Semiconductor Corporation
DS009515
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F299
O
c
t
a
l
Uni
versal
Shi
f
t
/
S
t
o
ra
ge Regi
ste
r
74F299
Octal Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The 74F299 is an 8-bit universal shift/storage register with
3-STATE outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel
load inputs and flip-flop outputs are multiplexed to reduce
the total number of package pins. Additional outputs, Q
0
Q
7
, are provided to allow easy serial cascading. A separate
active LOW Master Reset is used to reset the register.
Features
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load and
store
s
3-STATE outputs for bus-oriented applications
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F299SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F299SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F299PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com
2
74F299
Unit Loading/Fan Out
Functional Description
The 74F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S
0
and S
1
, as shown in
the Mode Select Table. All flip-flop outputs are brought out
through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE outputs are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
DS
0
Serial Data Input for Right Shift
1.0/1.0
20
A/
-
0.6 mA
DS
7
Serial Data Input for Left Shift
1.0/1.0
20
A/
-
0.6 mA
S
0
, S
1
Mode Select Inputs
1.0/2.0
20
A/
-
1.2 mA
MR
Asynchronous Master Reset Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
OE
1
, OE
2
3-STATE Output Enable Inputs (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
I/O
0
I/O
7
Parallel Data Inputs or
3.5/1.083
70
A/
-
0.65 mA
3-STATE Parallel Outputs
150/40(33.3)
-
3 mA/24 mA (20 mA)
Q
0
, Q
7
Serial Outputs
50/33.3
-
1 mA/20 mA
Inputs
Response
MR S
1
S
0
CP
L
X
X
X
Asynchronous Reset; Q
0
Q
7
=
LOW
H
H
H
Parallel Load; I/O
n
Q
n
H
L
H
Shift Right; DS
0
Q
0
, Q
0
Q
1
, etc.
H
H
L
Shift Left; DS
7
Q
7
, Q
7
Q
6
, etc.
H
L
L
X
Hold
3
www.fairchildsemi.com
7
4F299
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
ESD Last Passing Voltage (Min)
4000V
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
Current Applied to Output
-
0.5V to
+
5.5V
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA (Q
0
, Q
7
, I/O
n
)
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA (I/O
n
)
5% V
CC
2.7
I
OH
=
-
1 mA (Q
0
, Q
7
, I/O
n
)
5% V
CC
2.7
I
OH
=
-
3 mA (I/O
n
)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA (Q
0
, Q
7
)
Voltage
10% V
CC
0.5
I
OL
=
24 mA (I/O
n
)
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V (CP, DS
0
, DS
7
, S
0
, S
1
,
Current
MR, OE
1
, OE
2
)
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V (CP, DS
0
, DS
7
, S
0
, S
1
,
Breakdown Test
MR, OE
1
, OE
2
)
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V (I/O
n
)
Breakdown Test (I/O)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (CP, DS
0
, DS
7
, MR, OE
1
, OE
2
)
-
1.2
V
IN
=
0.5V (S
0
, S
1
)
I
IH
+
Output Leakage
70
A
Max
V
I/O
=
2.7V (I/O
n
)
I
OZH
Current
I
IL
+
Output Leakage
-
650
A
Max
V
I/O
=
0.5V (I/O
n
)
I
OZL
Current
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCH
Power Supply Current
68
95
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
68
95
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
68
95
mA
Max
V
O
=
HIGH Z
www.fairchildsemi.com
4
74F299
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0 to
+
70
C
Units
V
CC
=
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Input Frequency
70
100
85
70
MHz
t
PLH
Propagation Delay
4.0
7.0
8.0
4.0
9.0
4.0
8.5
ns
t
PHL
CP to Q
0
or Q
7
4.5
6.5
8.0
4.5
9.5
4.5
8.5
t
PLH
Propagation Delay
3.5
7.0
9.0
3.5
10.0
3.5
10.0
t
PHL
CP to I/O
n
4.0
8.5
9.0
4.0
11.0
4.0
10.0
t
PHL
Propagation Delay
5.5
7.5
9.5
5.5
12.5
5.5
10.5
ns
MR to Q
0
or Q
7
t
PHL
Propagation Delay
5.5
11.0
10.0
5.5
12.0
5.5
10.5
MR to I/O
n
t
PZH
Output Enable Time
3.5
6.0
8.0
3.0
9.5
3.5
9.0
ns
t
PZL
OE to I/O
n
4.0
7.0
10.0
4.0
13.0
4.0
11.0
t
PHZ
Output Disable Time
2.0
4.5
6.0
1.5
7.0
2.0
7.0
t
PLZ
OE to I/O
n
1.0
4.0
5.5
1.0
6.5
1.0
6.5
t
PZH
Output Enable Time
3.5
9.0
3.0
10.5
3.5
10.0
ns
t
PZL
S
n
to I/O
n
4.0
10.0
4.0
13.0
4.0
11.0
t
PHZ
Output Disable Time
2.5
6.0
1.5
7.0
2.5
7.0
ns
t
PLZ
S
n
to I/O
n
1.5
5.5
1.0
6.5
1.5
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0 to
+
70
C
Units
V
CC
=
5.0V
V
CC
=
5.0V
V
CC
=
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
8.5
10.0
8.5
ns
t
S
(L)
S
0
or S
1
to CP
8.5
7.5
8.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
0
t
H
(L)
S
0
or S
1
to CP
0
0
0
t
S
(H)
Setup Time, HIGH or LOW
5.0
5.0
5.0
ns
t
S
(L)
I/O
n
, DS
0
or DS
7
to CP
5.0
5.0
5.0
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.0
2.0
t
H
(L)
I/O
n
, DS
0
or DS
7
to CP
2.0
2.0
2.0
t
W
(H)
CP Pulse Width
5.0
5.0
5.0
ns
t
W
(L)
HIGH or LOW
5.0
5.0
5.0
t
W
(L)
MR Pulse Width, LOW
5.0
6.0
5.0
ns
t
REC
Recovery Time, MR to CP
7.0
12.0
7.0
ns
5
www.fairchildsemi.com
7
4F299
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number MD20D
www.fairchildsemi.com
6
74F29
9 Oct
a
l
Univer
sal
Shi
f
t
/
St
orage
Regis
t
er
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP