1999 Fairchild Semiconductor Corporation
DS009524
www.fairchildsemi.com
May 1988
Revised August 1999
7
4F374
O
c
t
a
l
D-T
ype
Fl
ip-
F
lo
p wit
h
3-ST
A
T
E Outp
uts
74F374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops.
Features
s
Edge-triggered D-type inputs
s
Buffered positive edge-triggered clock
s
3-STATE outputs for bus-oriented applications
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F374MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F374PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F374
Unit Loading/Fan Out
Functional Description
The 74F374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affected the state of the flip-
flops.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
D
7
Data Inputs
1.0/1.0
20
A/
-
0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
O
0
O
7
3-STATE Outputs
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Inputs
Internal
Output
D
n
CP
OE
Register
O
n
H
L
H
H
L
L
L
L
X
X
H
X
Z
3
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7
4F374
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCZ
Power Supply Current
55
86
mA
Max
V
O
=
HIGH Z
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4
74F374
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
100
140
60
70
MHz
t
PLH
Propagation Delay
4.0
6.5
8.5
4.0
10.5
4.0
10.0
ns
t
PHL
CP to O
n
4.0
6.5
8.5
4.0
11.0
4.0
10.0
t
PZH
Output Enable Time
2.0
9.0
11.5
2.0
14.0
2.0
12.5
ns
t
PZL
2.0
5.8
7.5
2.0
10.0
2.0
8.5
t
PHZ
Output Disable Time
2.0
5.3
7.0
2.0
8.0
2.0
8.0
t
PLZ
1.5
4.3
5.5
1.5
7.5
1.5
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.0
2.5
2.0
ns
t
S
(L)
D
n
to CP
2.0
2.0
2.0
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.0
2.0
t
H
(L)
D
n
to CP
2.0
2.5
2.0
t
W
(H)
CP Pulse Width
7.0
7.0
7.0
ns
t
W
(L)
HIGH or LOW
6.0
6.0
6.0
5
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7
4F374
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
74F374
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
7
www.fairchildsemi.com
7
4F374
O
c
t
a
l
D-T
ype
Fl
ip-
F
lo
p wit
h
3-ST
A
T
E Outp
uts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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