2000 Fairchild Semiconductor Corporation
DS005994
www.fairchildsemi.com
October 1987
Revised August 2000
CD451
4BC
CD4515BC
4
-
Bit
Latched/
4-
to-
16
L
i
ne Decoders
CD4514BC CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
The CD4514BC and CD4515BC are 4-to-16 line decoders
with latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. These circuits are prima-
rily used in decoding applications where low power dissipa-
tion and/or high noise immunity is required.
The CD4514BC (output active high option) presents a logi-
cal "1" at the selected output, whereas the CD4515BC pre-
sents a logical "0" at the selected output. The input latches
are RS type flip-flops, which hold the last input data pre-
sented prior to the strobe transition from "1" to "0". This
input data is decoded and the corresponding output is acti-
vated. An output inhibit line is also available.
Features
s
Wide supply voltage range:
3.0V to 15V
s
High noise immunity:
0.45 V
DD
(typ.)
s
Low power TTL:
fan out of 2
compatibility:
driving 74L
s
Low quiescent power dissipation:
0.025
W/package @ 5.0 V
DC
s
Single supply operation
s
Input impedance
=
10
12
typically
s
Plug-in replacement for MC14514, MC14515
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Top View
Order Number
Package Number
Package Diagram
CD4514BCWM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
CD4514BCN
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
CD4515BCWM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
CD4515BCN
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
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2
CD4514BC
C
D
45
15BC
Truth Table
Decode Truth Table (Strobe
=
1)
X
=
Don't Care
Logic Diagram
Data Inputs
Selected Output
Inhibit
D
C
B
A
CD4514
=
Logic "1"
CD4515
=
Logic "0"
0
0
0
0
0
S0
0
0
0
0
1
S1
0
0
0
1
0
S2
0
0
0
1
1
S3
0
0
1
0
0
S4
0
0
1
0
1
S5
0
0
1
1
0
S6
0
0
1
1
1
S7
0
1
0
0
0
S8
0
1
0
0
1
S9
0
1
0
1
0
S10
0
1
0
1
1
S11
0
1
1
0
0
S12
0
1
1
0
1
S13
0
1
1
1
0
S14
0
1
1
1
1
S15
1
X
X
X
X
All Outputs
=
0, CD4514
All Outputs
=
1, CD4515
3
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CD451
4BC
CD4515BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: "Absolute Maximum Ratings" are those values beyond which the
safety of the device cannot be guaranteed. Except for "Operating Tempera-
ture Range" they are not meant to imply that the devices should be oper-
ated at these limits. The tables of "Recommended Operating Conditions"
and "Electrical Characteristics" provide conditions for actual device opera-
tion.
Note 2: V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 2)
CD4514BC, CD4515BC
Note 3: I
OH
and I
OL
are tested one output at a time.
DC Supply Voltage (V
DD
)
-
0.5V to
+
18V
Input Voltage (V
IN
)
-
0.5V to V
DD
+
0.5V
Storage Temperature Range (T
S
)
-
65
C to
+
150
C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
DC Supply Voltage (V
DD
)
3V to 15V
Input Voltage (V
IN
)
0V to V
DD
Operating Temperature Range (T
A
)
CD4514BC,
CD4515BC
-
40
C to
+
85
C
Symbol
Parameter
Conditions
-
40
C
+
25
C
+
85
C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
=
5V, V
IN
=
V
DD
or V
SS
20
0.005
20
150
A
Current
V
DD
=
10V, V
IN
=
V
DD
or V
SS
40
0.010
40
300
A
V
DD
=
15V, V
IN
=
V
DD
or V
SS
80
0.015
80
600
A
V
OL
LOW Level
V
IL
=
0V, V
IH
=
V
DD
,
Output Voltage
|I
O
|
<
1
A
V
DD
=
5V
0.05
0
0.05
0.05
V
V
DD
=
10V
0.05
0
0.05
0.05
V
V
DD
=
15V
0.05
0
0.05
0.05
V
V
OH
HIGH Level
V
IL
=
0V, V
IH
=
V
DD
,
Output Voltage
|I
O
|
<
1
A
V
DD
=
5V
4.95
4.95
5.0
4.95
V
V
DD
=
10V
9.95
9.95
10.0
9.95
V
V
DD
=
15V
14.95
14.95
15.0
14.95
V
V
IL
LOW Level
|I
O
|
<
1
A
Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
1.5
2.25
1.5
1.5
V
V
DD
=
10V, V
O
=
1.0V or 9.0V
3.0
4.50
3.0
3.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
4.0
6.75
4.0
4.0
V
V
IH
HIGH Level
|I
O
|
<
1
A
Input Voltage
V
DD
=
5V, V
O
=
0.5V or 4.5V
3.5
3.5
2.75
3.5
V
V
DD
=
10V, V
O
=
1.0V or 9.0V
7.0
7.0
5.50
7.0
V
V
DD
=
15V, V
O
=
1.5V or 13.5V
11.0
11.0
8.25
11.0
V
I
OL
LOW Level Output
V
DD
=
5V, V
O
=
0.4V
0.52
0.44
0.88
0.36
mA
Current (Note 3)
V
DD
=
10V, V
O
=
0.5V
1.3
1.1
2.25
0.90
mA
V
DD
=
15V, V
O
=
1.5V
3.6
3.0
8.8
2.4
mA
I
OH
HIGH Level Output
V
DD
=
5V, V
O
=
4.6V
-
0.52
-
0.44
-
0.88
-
0.36
mA
Current (Note 3)
V
DD
=
10V, V
O
=
9.5V
-
1.3
-
1.1
-
2.25
-
0.90
mA
V
DD
=
15V, V
O
=
13.5V
-
3.6
-
3.0
-
8.8
-
2.4
mA
I
IN
Input Current
V
DD
=
15V, V
IN
=
0V
-
0.3
-
10
-
5
-
0.3
-
1.0
A
V
DD
=
15V, V
IN
=
15V
0.3
10
-
5
0.3
1.0
A
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4
CD4514BC
C
D
45
15BC
AC Electrical Characteristics
(Note 4)
All types C
L
=
50 pF, T
A
=
25
C, t
r
=
t
f
=
20 ns unless otherwise specified
Note 4: AC Parameters are guaranteed by DC correlated testing.
Note 5: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,
AN-90.
Note 6: Capacitance is guaranteed by periodic testing.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
THL
, t
TLH
Transition Times
V
DD
=
5V
100
200
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
40
80
ns
t
PLH
, t
PHL
Propagation Delay Times
V
DD
=
5V
550
1100
ns
V
DD
=
10V
225
450
ns
V
DD
=
15V
150
300
ns
t
PLH
, t
PHL
Inhibit Propagation
V
DD
=
5V
400
800
ns
Delay Times
V
DD
=
10V
150
300
ns
V
DD
=
15V
100
200
ns
t
SU
Setup Time
V
DD
=
5V
125
250
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
38
75
ns
t
WH
Strobe Pulse Width
V
DD
=
5V
175
350
ns
V
DD
=
10V
50
100
ns
V
DD
=
15V
38
75
ns
C
PD
Power Dissipation Capacitance
Per Package (Note 5)
150
pF
C
IN
Input Capacitance
Any Input (Note 6)
5
7.5
pF
5
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CD451
4BC
CD4515BC
AC Test Circuit and Switching Time Waveforms
FIGURE 1.
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6
CD4514BC
C
D
45
15BC
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch/decoder to effect a complex data
routing system. A total of 16 inputs from data registers are
selected and transferred via a 3-STATE data bus to a data
distributor for rearrangement and entry into 16 output regis-
ters. In this way sequential data can be re-routed or inter-
mixed according to patterns determined by data select and
distribution inputs.
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the 3-STATE data bus. A fourth
signal, labelled Dis, disables one of the CD4512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 116, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is 8
times faster than the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers.
Information from the 3-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INAIND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, AP. This distribution of data bits to the output
registers can be made in many complex patterns. For
example, all of the most significant bits from the input regis-
ters can be routed into output register A, all of the next
most significant bits into register B, etc. In this way horizon-
tal, vertical, or other methods of data slicing can be imple-
mented.
7
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CD451
4BC
CD4515BC
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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8
CD451
4BC
CD4515BC
4
-
Bit
Latched
/4-
t
o-
16
L
i
ne Decoders
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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