1999 Fairchild Semiconductor Corporation
DS009534
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F401 C
RC Generat
or/
C
hecker
74F401
CRC Generator/Checker
General Description
The 74F401 Cycle Redundancy Check (CRC) Generator/
Checker provides an advanced tool for implementing the
most widely used error detection scheme in serial digital
data handling systems. A 3-bit control input selects one-of-
eight generator polynomials. The list of polynomials
includes CRC-16 and CRC-CCITT as well as their recipro-
cals (reverse polynomials). Automatic right justification is
incorporated for polynomials of degree less than 16. Sepa-
rate clear and preset inputs are provided for floppy disk
and other applications. The Error output indicates whether
or not a transmission error has occurred. Another control
input inhibits feedback during check word transmission.
The 74F401 is fully compatible with all TTL families.
Features
s
Eight selectable polynomials
s
Error indicator
s
Separate preset and clear controls
s
Automatic right justification
s
Fully compatible with all TTL logic families
s
14-pin package
s
9401 equivalent
s
Typical applications:
Floppy and other disk storage systems
Digital cassette and cartridge systems
Data communication systems
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Order Number
Package Number
Package Description
74F401SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F401PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F401
Unit Loading/Fan Out
Functional Description
The 74F401 is a 16-bit programmable device which oper-
ates on serial data streams and provides a means of
detecting transmission errors. Cyclic encoding and decod-
ing schemes for error detection are based on polynomial
manipulation in modulo arithmetic. For encoding, the data
stream (message polynomial) is divided by a selected poly-
nomial. This division results in a remainder which is
appended to the message as check bits. For error check-
ing, the bit stream containing both data and check bits is
divided by the same selected polynomial. If there are no
detectable errors, this division results in a zero remainder.
Although it is possible to choose many generating polyno-
mials of a given degree, standards exist that specify a
small number of useful polynomials. The 74F401 imple-
ments the polynomials listed in Table 1 by applying the
appropriate logic levels to the select pins S
0,
S
1
and S
2
.
The 74F401 consists of a 16-bit register, a Read Only
Memory (ROM) and associated control circuitry as shown
in the block diagram. The polynomial control code pre-
sented at inputs S
0
, S
1
and S
2
is decoded by the ROM,
selecting the desired polynomial by establishing shift mode
operation on the register with Exclusive OR gates at appro-
priate inputs. To generate the check bits, the data stream is
entered via the Data inputs (D), using the HIGH-to-LOW
transition of the Clock input (CP). This data is gated with
the most significant output (Q) of the register, and controls
the Exclusive OR gates Figure 1. The Check Word Enable
(CWE) must be held HIGH while the data is being entered.
After the last data bit is entered, the CWE is brought LOW
and the check bits are shifted out of the register and
appended to the data bits using external gating Figure 2.
To check an incoming message for errors, both the data
and check bits are entered through the D input with the
CWE input held HIGH. The 74F401 is not in the data path,
but only monitors the message. The Error Output becomes
valid after the last check bit has been entered into the
74F401 by a HIGH-to-LOW transition of CP. If no detect-
able errors have occurred during the data transmission, the
resultant internal register bits are all LOW and the Error
Output (ER) is LOW. If a detectable error has occurred, ER
is HIGH.
A HIGH on the Master Reset input (MR) asynchronously
clears the register. A LOW on the Preset input (P) asyn-
chronously sets the entire register if the control code inputs
specify a 16-bit polynomial; in the case of 12- or 8-bit check
polynomials only the most significant 12 or 8 register bits
are set and the remaining bits are cleared.
TABLE 1.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
S
0
S
2
Polynomial Select Inputs
1.0/1.0
20
A/
-
0.6 mA
D
Data Input
1.0/1.0
20
A/
-
0.6 mA
CP
Clock Input (Operates on HIGH-to-LOW Transition)
1.0/1.0
20
A/
-
0.6 mA
CWE
Check Word Enable Input
1.0/1.0
20
A/
-
0.6 mA
P
Preset (Active LOW) Input
1.0/1.0
20
A/
-
0.6 mA
MR
Master Reset (Active HIGH) Input
1.0/1.0
20
A/
-
0.6 mA
Q
Data Output
50/33.3
-
1 mA/20 mA
ER
Error Output
50/33.3
-
1 mA/20 mA
Select Code
Polynomial
Remarks
S
2
S
1
S
0
L
L
L
X
16
+
X
15
+
X
2
+
1
CRC-16
L
L
H
X
16
+
X
14
+
X
+
1
CRC-16 REVERSE
L
H
L
X
16
+
X
15
+
X
13
+
X
7
+
X
4
+
X
2
+
X
1
+
1
L
H
H
X
12
+
X
11
+
X
3
+
X
2
+
X
+
1
CRC-12
H
L
L
X
8
+
X
7
+
X
5
+
X
4
+
X
+
1
H
L
H
X
8
+
1
LRC-8
H
H
L
X
16
+
X
12
+
X
5
+
1
CRC-CCITT
H
H
H
X
16
+
X
11
+
X
4
+
1
CRC-CCITT REVERSE
3
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7
4F401
Block Diagram
FIGURE 1. Equivalent Circuit for X
16
+
X
15
+
X
2
+
1
FIGURE 2. Check Word Generation
Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits.
Note 2: 74F401 must be reset or preset before each computation.
Note 3: CRC check bits are generated and appended to data bits.
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4
74F401
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
Note 4: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 5)
-
0.5V to
+
7.0V
Input Current (Note 5)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
5% V
CC
2.7
I
OH
=
-
1 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA
Voltage
I
IH
Input HIGH Current
5.0
A
Max
V
IN
=
2.7V
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CCH
Power Supply Current
70
105
mA
Max
V
O
=
HIGH
5
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7
4F401
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
100
85
MHz
t
PLH
Propagation Delay
4.5
11.5
4.5
13.5
ns
t
PHL
CP to Q
4.0
10.0
4.0
11.0
t
PHL
Propagation Delay
3.0
7.5
3.0
8.0
ns
MR to Q
t
PLH
Propagation Delay
3.0
8.5
3.0
9.5
ns
P to Q
t
PHL
Propagation Delay
3.5
11.0
3.5
12.0
ns
MR to ER
t
PLH
Propagation Delay
3.0
8.5
3.0
10.0
ns
P to ER
t
PLH
Propagation Delay
5.0
13.0
5.0
14.5
ns
t
PHL
CP to ER
4.5
11.5
4.5
12.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Set-up Time, HIGH or LOW
5.0
5.5
t
S
(L)
D to CP
5.0
5.5
t
S
(H)
Set-up Time, HIGH or LOW
4.0
4.5
ns
t
S
(L)
CWE to CP
4.0
4.5
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.0
t
H
(L)
D and CWE to CP
2.0
2.0
t
W
(L)
P Pulse Width, LOW
7.0
8.0
ns
t
W
(H)
Clock Pulse Width,
5.0
6.0
ns
t
W
(L)
HIGH or LOW
5.0
6.0
t
W
(H)
MR Pulse Width, HIGH
5.0
5.5
ns
t
REC
Recovery Time
4.0
4.5
ns
MR to CP
t
REC
Recovery Time
2.0
2.0
ns
P to CP
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