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Электронный компонент: 74F543SPC

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April 1988
Revised March 1999
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1999 Fairchild Semiconductor Corporation
DS009554.prf
www.fairchildsemi.com
74F543
Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA.
Features
s
8-bit octal transceiver
s
Back-to-back registers for storage
s
Separate controls for data flow in each direction
s
A outputs sink 24 mA
s
B outputs sink 64 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F543MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
74F543
Unit Loading/Fan Out
Functional Description
The F543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB)
input must be LOW in order to enter data from A
0
A
7
or
take data from B
0
B
7
, as indicated in the Data I/O Control
Table. With CEAB LOW, a LOW signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA,
LEBA and OEBA inputs.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
OEAB
A-to-B Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
OEBA
B-to-A Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
CEAB
A-to-B Enable Input (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
CEBA
B-to-A Enable Input (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
LEAB
A-to-B Latch Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
LEBA
B-to-A Latch Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
A
0
A
7
A-to-B Data Inputs or
3.5/1.083
70
A/
-
650
A
B-to-A 3-STATE Outputs
150/40 (33.8)
-
3 mA/24 mA (20 mA)
B
0
B
7
B-to-A Data Inputs or
3.5/1.083
70
A/
-
650
A
A-to-B 3-STATE Outputs
600/106.6 (80)
-
12 mA/64 mA (48 mA)
Inputs
Latch
Status
Output
Buffers
CEAB
LEAB
OEAB
H
X
X
Latched
High Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
High Z
L
X
L
--
Driving
3
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7
4F543
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
10% V
CC
2.5
I
OH
=
-
1 mA (A
n
)
10% V
CC
2.4
I
OH
=
-
3 mA (A
n
, B
n
)
5% V
CC
2.7
V
Min
I
OH
=
-
1 mA (A
n
)
5% V
CC
2.7
I
OH
=
-
3 mA (A
n
, B
n
)
10% V
CC
2.0
I
OH
=
-
15 mA (B
n
)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA (A
n
)
Voltage
10% V
CC
0.55
I
OL
=
64 mA (B
n
)
I
IH
Input HIGH Current
5.0
A
Max
V
IN
=
2.7V
I
BVI
Input HIGH Current
7.0
A
Max
(OEAB, OEBA, LEAB,
Breakdown Test
LEBA, CEAB, CEBA)
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (OEAB, OEBA)
-
1.2
V
IN
=
0.5V (CEAB, CEBA)
I
IH
+
I
OZH
Output Leakage Current
70
A
Max
V
OUT
=
2.7V (A
n
, B
n
)
I
IL
+
I
OZL
Output Leakage Current
-
650
A
Max
V
OUT
=
0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V (A
n
)
-
100
-
225
V
OUT
=
0V (B
n
)
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V (A
n
, B
n
)
I
CCH
Power Supply Current
67
100
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
83
125
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
83
125
mA
Max
V
O
=
HIGH Z
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4
74F543
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
Units
V
CC
=
+
5.0V
T
A
=
0
C to
+
70
C
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.0
5.5
7.5
3.0
8.5
t
PHL
Transparent Mode
3.0
5.0
6.5
3.0
7.5
ns
A
n
to B
n
or B
n
to A
n
t
PLH
Propagation Delay
4.5
8.5
11.0
4.5
12.5
ns
t
PHL
LEBA to A
n
4.5
8.5
11.0
4.5
12.5
t
PLH
Propagation Delay
4.5
8.5
11.0
4.5
12.5
ns
t
PHL
LEAB to B
n
4.5
8.5
11.0
4.5
12.5
t
PZH
Output Enable Time
t
PZL
OEBA or OEAB to A
n
or B
n
3.0
7.0
9.0
3.0
10.0
CEBA or CEAB to A
n
or B
n
4.0
7.5
10.5
4.0
12.0
ns
t
PHZ
Output Disable Time
t
PLZ
OEBA or OEAB to A
n
or B
n
1.0
6.0
8.0
1.0
9.0
CEBA or CEAB to A
n
or B
n
2.5
5.5
10.5
2.5
11.5
Symbol
Parameter
T
A
=
+
25
C
Units
V
CC
=
+
5.0V
T
A
=
0
C to
+
70
C
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
3.0
3.5
t
S
(L)
A
n
or B
n
to LEBA or LEAB
3.0
3.5
ns
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
t
H
(L)
A
n
or B
n
to LEBA or LEAB
3.0
3.5
t
W
(L)
Latch Enable, B to A or
8.0
9.0
ns
B to A Pulse Width, LOW
5
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7
4F543
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
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6
74F543
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7
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LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C