2000 Fairchild Semiconductor Corporation
DS009561
www.fairchildsemi.com
April 1988
Revised March 2000
7
4F552
O
c
t
a
l
Regi
ster
ed T
r
anscei
ver
wit
h
Pa
rit
y
and Fl
ags
74F552
Octal Registered Transceiver with Parity and Flags
General Description
The 74F552 octal transceiver contains two 8-bit registers
for temporary storage of data flowing in either direction.
Each register has its own clock pulse and clock enable
input as well as a flag flip-flop that is set automatically as
the register is loaded. The flag output will be reset when
the output enable returns to HIGH after reading the output
port. Each register has a separate output enable control for
its 3-STATE buffer. The separate Clocks, Flags, and
Enables provide considerable flexibility as I/O ports for
demand-response data transfer. When data is transferred
from the A Port to the B Port, a parity bit is generated. On
the other hand, when data is transferred from the B Port to
the A Port, the parity of input data on B
0
B
7
is checked.
Features
s
8-Bit bidirectional I/O Port with handshake
s
Register status flag flip-flops
s
Separate clock enable and output enable
s
Parity generation and parity check
s
B-outputs sink 64 mA
s
3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
Pin Assignments for SOIC
Pin Assignments for PLCC
Order Number
Package Number
Package Description
74F552SC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F552QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
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2
74F552
Logic Symbols
IEEE/IEC
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
A
7
A-to-B Port Data Inputs or
3.5/1.083
70
A/
-
0.65 mA
B-to-A 3-STATE
150/40 (33.3)
-
3 mA/24 mA (20 mA)
B
0
B
7
B-to-A Transceiver Inputs or
3.5/1.083
70
A/
-
0.65 mA
A-to-B 3-STATE Output
600/106.6 (80)
-
12 mA/64 mA (48 mA)
FR
B Port Flag Output
50/33.3
-
1 mA/20 mA
FS
A Port Flag Output
50/33.3
-
1 mA/20 mA
PARITY
Parity Bit Transceiver Input or Output
3.5/1.083
70
A/
-
0.65 mA
600/106.6 (50)
-
12 mA/64 mA (48 mA)
ERROR
Parity Check Output (Active LOW)
50/33.3
-
1 mA/20 mA
CER
R Registers Clock Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
CES
S Registers Clock Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
CPR
R Registers Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
CPS
S Registers Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
OEBR
B Port and PARITY Output Enable (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
and Clear FR Input (Active Rising Edge)
OEAS
A Port Output Enable (Active LOW)
1.0/2.0
20
A/
-
1.2 mA
and Clear FS Input (Active Rising Edge)
3
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7
4F552
Functional Description
Data applied to the A-inputs are entered and stored in the
R register on the rising edge of the CPR Clock Pulse, pro-
vided that the Clock Enable (CER) is LOW; simultaneously,
the status flip-flop is set and the flag (FR) output goes
HIGH. As the Clock Enable (CER) returns to HIGH, the
data will be held in the R register. These data entered from
the A-inputs will appear at the B Port I/O pins after the Out-
put Enable (OEBR) has gone LOW. When OEBR is LOW,
a parity bit appears at the PARITY pin, which will be set
HIGH when there is an even number of 1s or all 0s at the Q
outputs of the R register. After the data is assimilated, the
receiving system clears the flag FR by changing the signal
at the OEBR pin from LOW-to-HIGH.
Data flow from B-to-A proceeds in the same manner
described for A-to-B flow. A LOW at the CES pin and a
LOW-to-HIGH transition at CPS pin enters the B-input data
and the parity-input data into the S registers and the parity
register respectively and set the flag output FS to HIGH. A
LOW signal at the OEAS pin enables the A Port I/O pins
and a LOW-to-HIGH transition of the OEAS signal clears
the FS flag. When OEAS is LOW, the parity check output
ERROR will be HIGH if there is an odd number of 1s at the
Q outputs of the S registers and the parity register. The flag
FS can be cleared by a LOW-to-HIGH transition of the
OEAS signal.
Register Function Table
(Applies to R or S Register)
H
=
HIGH Voltage Level
=
LOW-to-HIGH Transition
L
=
LOW Voltage Level
=
Not LOW-to-HIGH Transition
X
=
Immaterial
NC
=
No Change
Output Control
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
Z
=
High Impedance
Flag Flip-Flop Function Table
(Applies to R or S Flag Flip-Flop)
H
=
HIGH Voltage Level
=
LOW-to-HIGH Transition
L
=
LOW Voltage Level
=
Not LOW-to-HIGH Transition
X
=
Immaterial
NC
=
No Change
Parity Generation Function
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
Z
=
High Impedance
Parity Check Function
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Inputs
Internal
Function
D
CP
CE
Q
X
X
H
NC
Hold Data
L
L
L
Load Data
H
L
H
X
L
NC
Keep Old Data
OE
Internal
A or B
Function
Q
Outputs
H
X
Z
Disable Output
L
L
L
Enable Output
L
H
H
Enable Output
Inputs
Flag
Function
CE
CP
OE
Output
H
X
NC
Hold Flag
L
H
Set Flag
X
X
L
Clear Flag
OEBR
Number of HIGHs in the
Parity Output
Q Outputs of the R Register
H
X
Z
L
0, 2, 4, 6, 8
H
L
1, 3, 5, 7
L
OEAS
Number of HIGHs in
Parity
ERROR
the Q Outputs of the S Register
Input
Output
H
X
X
H
L
0, 2, 4, 6, 8
L
L
L
1, 3, 5, 7
L
H
L
0, 2, 4, 6, 8
H
H
L
1, 3, 5, 7
H
L
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4
74F552
Block Diagram
5
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7
4F552
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
175
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode
-
1.2
V
Min
I
IN
=
-
18 mA
Voltage
(CER, CES, CPR, CPS, OEBR, OEAS)
V
OH
Output HIGH
10% V
CC
2.5
I
OH
=
-
1 mA (FR, FS, ERROR, A
n
)
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA (A
n
, B
n
PARITY)
10% V
CC
2.0
V
Min
I
OH
=
-
15 mA (B
n
, PARITY)
5% V
CC
2.7
I
OH
=
-
1 mA (FR, FS, ERROR, A
n
)
5% V
CC
2.7
I
OH
=
-
3 mA (A
n
, B
n
, PARITY)
V
OL
Output LOW
10% V
CC
0.5
I
OL
=
20 mA (FR, FS, ERROR)
Voltage
10% V
CC
0.5
V
Min
I
OL
=
24 mA (A
n
)
10% V
CC
0.55
I
OL
=
64 mA (B
n
, PARITY)
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
(CER, CES, CPR, CPS, OEBR, OEAS)
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
(CER, CES, CPR, CPS, OEBR, OEAS)
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V
Breakdown (I/O)
(A
n
, B
n
, PARITY)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
(FR, FS, ERROR, A
n
, B
n
, PARITY)
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All other pins grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All other pins grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (CER, CES, CPR, CPS)
-
1.2
V
IN
=
0.5V (OEBR, OEAS)
I
IH
+
I
OZH
Output Leakage Current
70
A
Max
V
OUT
=
2.7V (A
n
, B
n
, PARITY)
I
IL
+
I
OZL
Output Leakage Current
-
650
A
Max
V
OUT
=
0.5V (A
n
, B
n
, PARITY)
I
OS
Output Short-
-
60
-
175
mA
Max
V
OUT
=
0V (FR, FS, ERROR, A
n
)
Circuit Current
-
100
-
250
V
OUT
=
0V (B
n
, PARITY)
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V (A
n
, B
n
, PARITY)
I
CCH
Power Supply Current
100
150
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
100
150
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
110
165
mA
Max
V
O
=
HIGH Z
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6
74F552
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.5
6.0
8.0
3.0
9.0
ns
t
PHL
CPS or CPR to A
n
or B
n
4.0
7.0
9.5
3.5
10.5
t
PLH
Propagation Delay
3.0
5.5
7.5
2.5
8.5
ns
CPS or CPR to FS or FR
t
PHL
Propagation Delay
3.5
6.0
8.0
3.0
9.0
ns
OEAS to FS
t
PLH
Propagation Delay
8.0
14.0
18.0
7.0
20.0
ns
t
PHL
CPR to Parity
8.5
14.5
18.5
7.5
20.5
t
PLH
Propagation Delay
8.0
13.5
17.5
7.0
19.5
ns
t
PHL
CPS to ERROR
7.5
13.0
16.5
6.5
18.5
t
PLH
Propagation Delay
3.5
6.0
8.0
3.0
9.0
ns
t
PHL
OEAS to ERROR
3.0
5.0
7.0
2.5
8.0
t
PZH
Enable Time OEAS
3.0
5.5
7.5
2.5
8.5
ns
t
PZL
or OEBR to B
n
or A
n
3.5
7.0
9.5
3.0
10.5
t
PHZ
Disable Time OEAS
3.0
6.5
8.5
2.5
9.5
t
PLZ
or OEBR to B
n
or A
n
3.0
5.5
7.5
2.5
8.5
t
PZH
Enable Time
3.0
4.5
7.5
2.5
8.5
ns
t
PZL
OEBR to Parity
3.5
6.0
9.5
3.0
10.5
t
PHZ
Disable Time
3.0
5.5
8.5
2.5
9.5
t
PLZ
OEBR to Parity
3.0
6.5
7.5
2.5
8.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
7.5
8.5
ns
t
S
(L)
A
n
or B
n
or Parity
4.5
5.0
to CPS or CPR
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
A
n
or B
n
or Parity
0
0
to CPS or CPR
t
S
(H)
Setup, Time HIGH or LOW
6.0
7.0
ns
t
S
(L)
CES or CER to CPS or CPR
10.0
11.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
CES or CER to CPS or CPR
0
0
t
W
(H)
Pulse Width, HIGH or LOW
4.0
4.5
ns
t
W
(L)
CPS or CPR
6.0
7.0
7
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7
4F552
Physical Dimensions
inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M28B
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8
74F552 Octal
Regi
st
ered T
r
ans
ceiver
wi
th Pari
ty and Flags
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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