1999 Fairchild Semiconductor Corporation
DS009563
www.fairchildsemi.com
April 1983
Revised August 1999
7
4F564
O
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t
a
l
D-T
ype
Fl
ip-
F
lo
p wit
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3-ST
A
T
E Outp
uts
74F564
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F564 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Out-
put Enable (OE). The information presented to the D inputs
is sorted in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
This device is functionally identical to the 74F574, but has
inverted outputs.
Features
s
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to 74F574
s
3-STATE outputs for bus-oriented applications
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F564SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F564PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F564
Unit Loading/Fan Out
Functional Description
The 74F564 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
H
=
HIGH Voltage Level
Z
=
High Impedance
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition
X
=
Immaterial
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
D
7
Data Inputs
1.0/1.0
20
A/
-
0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
O
0
O
7
3-STATE Outputs
150/40 (33.3)
-
3 mA/24 mA (20 mA)
Inputs
Internal Outputs
Function
OE
CP
D
Q
O
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L
H
Z
Load
H
H
L
Z
Load
L
L
H
H
Data Available
L
H
L
L
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
3
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7
4F564
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA
5% V
CC
2.7
I
OH
=
-
1 mA
5% V
CC
2.7
I
OH
=
-
3 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCZ
Power Supply Current
55
86
mA
Max
V
O
=
HIGH Z
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4
74F564
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
100
70
MHz
t
PLH
Propagation Delay
2.5
5.2
8.5
2.5
8.5
ns
t
PHL
CP to O
n
2.5
5.9
8.5
2.5
8.5
t
PZH
Output Enable Time
3.0
5.6
9.0
2.5
10.0
ns
t
PZL
3.0
6.2
9.0
2.5
10.0
t
PHZ
Output Disable Time
1.5
3.4
5.5
1.5
6.5
t
PLZ
1.5
2.7
5.5
1.5
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.0
2.0
ns
t
S
(L)
D
n
to CP
2.5
2.5
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.0
t
H
(L)
D
n
to CP
2.0
2.0
t
W
(H)
CP Pulse Width
5.0
5.0
ns
t
W
(L)
HIGH or LOW
5.0
5.0
5
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7
4F564
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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