1999 Fairchild Semiconductor Corporation
DS009565
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F569 4-Bi
t Bidi
rect
iona
l Counter
wi
th 3-ST
A
T
E
Out
puts
74F569
4-Bit Bidirectional Counter with 3-STATE Outputs
General Description
The 74F569 is a fully synchronous, reversible counter with
3-STATE outputs. The 74F569 is a binary counter, featur-
ing preset capability for programmable operation, carry loo-
kahead for easy cascading, and a U/D input to control the
direction of counting. For maximum flexibility there are both
synchronous and master asynchronous reset inputs as well
as both Clocked Carry (CC) and Terminal Count (TC) out-
puts. All state changes except Master Reset are initiated by
the rising edge of the clock. A HIGH signal on the Output
Enable (OE) input forces the output buffers into the high
impedance state but does not prevent counting, resetting
or parallel loading.
Features
s
Synchronous counting and loading
s
Lookahead carry capability for easy cascading
s
Preset capability for programmable operation
s
3-STATE outputs for bus organized systems
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
FAST
is a registered trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74F569SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F569SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F569PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F569
Unit Loading/Fan Out
Functional Description
The 74F569 counts in the modulo-16 binary sequence.
From state 15 it will increment to state 0 in the Up mode; in
the Down mode it will decrement from 0 to 15. The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. All state changes (except due to Master Reset)
occurs synchronously with the LOW-to-HIGH transition of
the Clock Pulse (CP) input signal.
The circuits have five fundamental modes of operation, in
order of precedence: asynchronous reset, synchronous
reset, parallel load, count and hold. Five control inputs--
Master Reset (MR), Synchronous Reset (SR), Parallel
Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle CET)--plus the Up/Down (U/D) input, deter-
mine the mode of operation, as shown in the Mode Select
Table. A LOW signal on MR overrides all other inputs and
asynchronously forces the flip-flop Q outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows the Q outputs to go LOW on the next rising edge of
CP. A LOW signal on PE overrides counting and allows
information on the Parallel Data (P
n
) inputs to be loaded
into the flip-flops on the next rising edge of CP. With MR,
SR and PE HIGH, CEP and CET permit counting when
both are LOW. Conversely, a HIGH signal on either CEP or
CET inhibits counting.
The 74F569 uses edge-triggered flip-flops and changing
the SR, PE, CEP, CET or U/D inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
HIGH and goes LOW providing CET is LOW, when the
counter reaches zero in the Down mode, or reaches maxi-
mum
(15) in the Up mode. TC will then remain LOW until a state
change occurs, whether by counting or presetting, or until
U/D or CET is changed. To implement synchronous multi-
stage counters, the connections between the TC output
and the CEP and CET inputs can provide either slow or
fast carry propagation.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min in
the Up mode, or min to max in the Down mode, to start its
final cycle. Since this final cycle takes 16 clocks to com-
plete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters. For such applications, the Clocked Carry (CC)
output is provided. The CC output is normally HIGH. When
CEP, CET, and TC are LOW, the CC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again, as shown in the CC Truth Table.
When the Output Enable (OE) is LOW, the parallel data
outputs O
0
O
3
are active and follow the flip-flop Q outputs.
A HIGH signal on OE forces O
0
O
3
to the High Z state but
does not prevent counting, loading or resetting.
Logic Equations
Count Enable
=
CEP CET PE
Up: TC
=
Q
0
Q
1
Q
2
Q
3
(Up) CET
Down: TC
=
Q
0
Q
1
Q
2
Q
3
(Down) CET
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
P
0
P
3
Parallel Data Inputs
1.0/1.0
20
A/
-
0.6 mA
CEP
Count Enable Parallel Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
CET
Count Enable Trickle Input (Active LOW)
1.0/1.0
20
A/
-
1.2 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
PE
Parallel Enable Input (Active LOW)
1.0/1.0
20
A/
-
1.2 mA
U/D
Up/Down Count Control Input
1.0/1.0
20
A/
-
0.6 mA
OE
Output Enable Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
MR
Master Reset Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
SR
Synchronous Reset Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
O
0
O
3
3-STATE Parallel Data Outputs
150/40(33.3)
-
3 mA/24 mA (20 mA)
TC
Terminal Count Output (Active LOW)
50/33.3
-
1 mA/20 mA
CC
Clocked Carry Output (Active LOW)
50/33.3
-
1 mA/20 mA
3
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7
4F569
CC Truth Table
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
=
HIGH-to-LOW-to-HIGH Clock Transition
Note 1: TC is generated internally
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
State Diagram
Inputs
Output
SR
PE
CEP CET
TC
(Note 1)
CP
CC
L
X
X
X
X
X
H
X
L
X
X
X
X
H
X
X
H
X
X
X
H
X
X
X
H
X
X
H
X
X
X
X
H
X
H
H
H
L
L
L
Inputs
Operating
MR
SR
PE
CEP CET
U/D
Mode
L
X
X
X
X
X
Asynchronous Reset
H
L
X
X
X
X
Synchronous Reset
H
H
L
X
X
X
Parallel Load
H
H
H
H
X
X
Hold
H
H
H
X
H
X
Hold
H
H
H
L
L
H
Count Up
H
H
H
L
L
L
Count Down
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4
74F569
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
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7
4F569
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
175
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA (TC, CC, O
n
)
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA (O
n
)
5% V
CC
2.7
I
OH
=
-
1 mA (TC, CC, O
n
)
5% V
CC
2.7
I
OH
=
-
3 mA (O
n
)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA (TC, CC)
Voltage
10% V
CC
0.5
I
OL
=
24 mA (O
n
)
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
(TC, CC, O
n
)
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (P
n
, CEP, CP, U/D, OE, MR, SR)
-
1.2
mA
Max
V
IN
=
0.5V (PE, CET)
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V (O
n
)
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V (O
n
)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V (TC, CC, O
n
)
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V (O
n
)
I
CCH
Power Supply Current
45
67
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
45
67
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
45
67
mA
Max
V
O
=
HIGH Z
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6
74F569
AC Electrical Characteristics
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
90
70
MHz
t
PLH
Propagation Delay
3.0
6.5
8.5
3.0
9.5
ns
t
PHL
CP to O
n
(PE HIGH or LOW)
4.0
9.0
11.5
4.0
13.0
t
PLH
Propagation Delay
5.5
12.0
15.5
5.5
17.5
ns
t
PHL
CP to TC
4.0
8.5
12.5
4.0
13.0
t
PLH
Propagation Delay
2.5
4.5
6.5
2.5
7.0
ns
t
PHL
CET to TC
2.5
6.0
11.0
2.5
12.0
t
PLH
Propagation Delay
3.5
8.5
11.5
3.5
12.5
ns
t
PHL
U/D to TC
4.0
8.0
12.0
4.0
13.0
t
PLH
Propagation Delay
2.5
5.5
7.0
2.0
8.0
ns
t
PHL
CP to CC
2.0
4.5
6.0
2.0
7.0
t
PLH
Propagation Delay
2.5
5.0
6.5
2.0
7.5
ns
t
PHL
CEP, CET to CC
4.0
8.5
11.0
4.0
12.5
t
PHL
Propagation Delay
5.0
10.0
13.0
5.0
14.5
ns
MR to O
n
t
PZH
Output Enable Time
2.5
5.5
8.0
2.5
8.5
ns
t
PZL
OE to O
n
3.0
6.0
9.0
3.0
10.0
t
PHZ
Output Disable Time
1.5
5.0
7.0
1.5
8.0
t
PLZ
OE to O
n
2.0
4.5
6.0
2.0
7.0
7
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7
4F569
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
4.0
4.5
ns
t
S
(L)
P
n
to CP
4.0
4.5
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
t
H
(L)
P
n
to CP
3.0
3.5
t
S
(H)
Setup Time, HIGH or LOW
7.0
8.0
ns
t
S
(L)
CEP or CET to CP
5.0
6.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
CEP or CET to CP
0.5
0.5
t
S
(H)
Setup Time, HIGH or LOW
8.0
9.0
ns
t
S
(L)
PE to CP
8.0
9.0
t
H
(H)
Hold Time, HIGH or LOW
0.0
1.0
t
H
(L)
PE to CP
0
0
t
S
(H)
Setup Time, HIGH or LOW
11.0
12.5
ns
t
S
(L)
U/D to CP
7.0
8.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
ns
t
H
(L)
U/D to CP
0
0
t
S
(H)
Setup Time, HIGH or LOW
10.5
11.0
ns
t
S
(L)
SR to CP
8.5
9.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
SR to CP
0
0
t
W
(H)
CP Pulse Width,
4.0
4.5
ns
t
W
(L)
HIGH or LOW
7.0
8.0
t
W
(L)
MR Pulse Width, LOW
4.5
6.0
ns
t
REC
MR Recovery Time
6.0
8.0
ns
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8
74F569
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
9
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7
4F569 4-Bi
t Bidi
rect
iona
l Counter
wi
th 3-ST
A
T
E
Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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