1999 Fairchild Semiconductor Corporation
DS009568
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F579 8-Bi
t Bidi
rect
iona
l Binar
y
Count
er wit
h
3-
ST
A
T
E Output
s
74F579
8-Bit Bidirectional Binary Counter with 3-STATE Outputs
General Description
The 74F579 is a fully synchronous 8-stage up/down
counter with multiplexed 3-STATE I/O ports for bus-ori-
ented applications. It features a preset capability for pro-
grammable operation, carry lookahead for easy cascading
and a U/D input to control the direction of counting. All state
changes, whether in counting or parallel loading, are initi-
ated by the rising edge of the clock.
Features
s
Multiplexed 3-STATE I/O ports
s
Built-in lookahead carry capability
s
Count frequency 100 MHz typical
s
Supply current 75 mA typical
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code.
Logic Symbol
Connection Diagram
Order Number
Package Number
Package Description
74F579SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F579SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F579PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74F579
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Not LL = CS and PE should never both be LOW voltage level at the same time.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
I/O
0
I/O
7
Data Inputs or
3.5/0.333
70
A/
-
0.2 mA
3-STATE Outputs
75/15
-
3 mA/24 mA
PE
Parallel Enable Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
U/D
Up-Down Count Control Input
0.25/0.333
5
A/
-
0.2 mA
MR
Master Reset Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
SR
Synchronous Reset Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
CEP
Count Enable Parallel Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
CET
Count Enable Trickle Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
CS
Chip Select Input Active (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
OE
Output Enable Input (Active LOW)
0.25/0.333
5
A/
-
0.2 mA
CP
Clock Pulse Input (Active Rising Edge)
0.25/0.333
5
A/
-
0.2 mA
TC
Terminal Count Output (Active LOW)
25/12.5
-
1 mA/5 mA
MR
SR
CS
PE
CEP CET U/D
OE
CP
Function
X
X
H
X
X
X
X
X
X
I/O
a
to I/O
h
in High Z (PE Disabled)
X
X
L
H
X
X
X
H
X
I/O
a
to I/O
h
in High Z
X
X
L
H
X
X
X
L
X
Flip-Flop Outputs Appear on I/O Lines
L
X
X
X
X
X
X
X
X
Asynchronous Reset for all Flip-Flops
H
L
X
X
X
X
X
X
Synchronous Reset for all Flip-Flops
H
H
L
L
X
X
X
X
Parallel Load all Flip-Flops
H
H
(Not LL)
H
X
X
X
Hold
H
H
(Not LL)
X
H
X
X
Hold (TC Held HIGH)
H
H
(Not LL)
L
L
H
X
Count Up
H
H
(Not LL)
L
L
L
X
Count Down
3
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7
4F579
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
V
CC
=
Pin 16
GND
=
Pin 6
()
=
Pin Numbers
Detail A
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4
74F579
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.4
V
Min
I
OH
=
-
3 mA
Voltage
5% V
CC
2.7
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA (TC), I
OL
=
24 mA (I/O
n
)
Voltage
5% V
CC
0.5
I
OL
=
20 mA (TC), I
OL
=
24 mA (I/O
n
)
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V (Non-I/O Pins)
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V (Non-I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V (I/O
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Control
All Other Pins Grounded
I
ZZ
Bus Drainage Test
500
A
0.0
V
OUT
=
5.25V
I
IL
Input LOW Current
-
0.2
mA
Max
V
IN
=
0.5V (Non-I/O Pins)
I
IH
& I
OZH
Output Leakage Current
70
A
Max
V
OUT
=
2.7V (I/O
n
)
I
IL
& I
OZL
Output Leakage Current
-
200
A
Max
V
OUT
=
0.5V (I/O
n
)
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CCH
Power Supply Current
70
110
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
85
120
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
85
125
mA
Max
V
O
=
HIGH Z
5
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7
4F579
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
70
85
80
t
PLH
Propagation Delay
3.0
5.0
7.5
3.0
8.0
ns
t
PHL
CP to I/O
n
5.0
8.0
11.5
5.0
11.5
t
PLH
Propagation Delay
5.0
7.5
11.5
5.0
12.0
ns
t
PHL
CP to TC
5.0
7.0
11.5
5.0
12.0
t
PLH
Propagation Delay
4.5
7.0
9.0
4.5
10.0
ns
t
PHL
U/D to TC
4.5
8.0
9.5
4.5
10.0
t
PLH
Propagation Delay
2.5
3.8
6.0
2.5
6.5
ns
t
PHL
CEP or CET to TC
3.5
6.0
8.0
3.5
8.5
t
PHL
Propagation Delay
5.0
7.5
10.0
5.0
10.0
ns
MR to I/O
n
t
PHL
Propagation Delay
6.5
10.0
13.0
6.5
13.5
ns
MR to TC
t
PZH
Output Enable Time
3.0
5.0
8.5
3.0
9.0
ns
t
PZL
CS or PE to I/O
5.5
8.0
10.5
5.5
11.5
t
PHZ
Output Disable Time
2.0
5.0
8.5
2.0
9.0
ns
t
PLZ
CS or PE to I/O
2.0
4.5
8.0
2.0
8.5
t
PZH
Output Enable Time
3.0
5.0
8.0
3.0
8.5
ns
t
PZL
OE to I/O
n
5.0
8.0
11.0
5.0
12.0
t
PHZ
Output Disable Time
2.0
4.0
6.5
2.0
6.5
ns
t
PLZ
OE to I/O
n
2.0
4.0
6.0
2.0
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Typ
Max
Min
Max
t
S
(H)
Setup Time
4.0
4.0
ns
t
S
(L)
I/O
n
to CP
4.0
4.0
t
H
(H)
Hold Time
0.0
0.0
ns
t
H
(L)
I/O
n
to CP
0.0
0.0
t
S
(H)
Setup Time
9.5
9.5
ns
t
S
(L)
PE, CS or SR to CP
9.5
9.5
t
H
(H)
Hold Time
0.0
0.0
ns
t
H
(L)
PE, CS or SR to CP
0.0
0.0
t
S
(H)
Setup Time
6.5
6.5
ns
t
S
(L)
CET or CEP to CP
9.5
9.5
t
H
(H)
Hold Time
0.0
0.0
ns
t
H
(L)
CET or CEP to CP
0.0
0.0
t
S
(H)
Setup Time
9.0
9.5
ns
t
S
(L)
U/D to CP
9.0
9.5
t
H
(H)
Hold Time
0.0
0.0
ns
t
H
(L)
U/D to CP
0.0
0.0
t
W
(H)
Clock Pulse Width
4.5
4.5
ns
t
W
(L)
HIGH or LOW
4.5
4.5
t
W
(L)
MR Pulse Width
3.0
3.0
ns
t
REC
Recovery Time
4.0
4.0
ns
MR to CP
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6
74F579
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
www.fairchildsemi.com
7
4F579 8-Bi
t Bidi
rect
iona
l Binar
y
Count
er wit
h
3-
ST
A
T
E Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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