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Электронный компонент: 74LCX16500CW

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2002 Fairchild Semiconductor Corporation
DS012407
www.fairchildsemi.com
March 1995
Revised June 2002
7
4
LCX16500 Low
V
o
lt
age 18-Bi
t Univer
sal

Bus T
r
ansc
eiver
s
wi
th 5V
T
o
l
e
ran
t
Input
s
a
nd
Out
puts
74LCX16500
Low Voltage 18-Bit Universal Bus Transceivers with
5V Tolerant Inputs and Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX16500 is designed for low voltage (2.5V or 3.3V)
V
CC
applications with the capability of interfacing to a 5V
signal environment.
The LCX16500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
s
5V tolerant inputs and outputs
s
2.3V3.6V V
CC
specifications provided
s
6.0 ns t
PD
max (V
CC
=
3.3V), 20
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
24 mA output drive (V
CC
=
3.0V)
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering code "G" indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
74LCX16500G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LCX16500MEA
(Note 3)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX16500MTD
(Note 3)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74LCX16500
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Table
(Note 4)
Note 4: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 5: Output level before the indicated steady-state input conditions
were established.
Note 6: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
Functional Description
For A-to-B data flow, the LCX16500 operates in the trans-
parent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a HIGH or LOW
logic level. If LEAB is LOW, the A bus data is stored in the
latch/flip-flop on the HIGH-to-LOW transition of CLKAB.
Output-enable OEAB is active-HIGH. When OEAB is
HIGH, the outputs are active. When OEAB is LOW, the out-
puts are in the high impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
Pin Names
Description
A
1
- A
18
Data Register A Inputs/3-STATE Outputs
B
1
- B
18
Data Register B Inputs/3-STATE Outputs
CLKAB, CLKBA Clock Pulse Inputs
LEAB, LEBA
Latch Enable Inputs
OEBA, OEBA
Output Enable Inputs
1
2
3
4
5
6
A
A
2
A
1
OEAB
GND
B
1
B
2
B
A
4
A
3
LEAB
CLKAB
B
3
B
4
C
A
6
A
5
V
CC
V
CC
B
5
B
6
D
A
8
A
7
GND
GND
B
7
B
8
E
A
10
A
9
GND
GND
B
9
B
10
F
A
12
A
11
GND
GND
B
11
B
12
G
A
14
A
13
V
CC
V
CC
B
13
B
14
H
A
16
A
15
OEBA CLKBA
B
15
B
16
J
A
17
A
18
LEBA
GND
B
18
B
17
Inputs
Output
OEAB
LEAB
CLKAB
A
n
B
n
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B
0
(Note 5)
H
L
L
X
B
0
(Note 6)
3
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7
4
LCX16500
Logic Diagram
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4
74LCX16500
Absolute Maximum Ratings
(Note 7)
Recommended Operating Conditions
(Note 9)
Note 7: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 8: I
O
Absolute Maximum Rating must be observed.
Note 9: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
7.0
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to V
CC
+
0.5
Output in HIGH or LOW State (Note 8)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
+
50
V
O
>
V
CC
I
O
DC Output Source/Sink Current
50
mA
I
CC
DC Supply Current per Supply Pin
100
mA
I
GND
DC Ground Current per Ground Pin
100
mA
T
STG
Storage Temperature
-
65 to
+
150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
=
3.0V
-
3.6V
24
mA
V
CC
=
2.7V
-
3.0V
12
V
CC
=
2.3V
-
2.7V
8
T
A
Free-Air Operating Temperature
-
40
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
C to
+
85
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3
-
2.7
1.7
V
2.7
-
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
-
2.7
0.7
V
2.7
-
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
2.3
-
3.6
V
CC
-
0.2
V
I
OH
=
-
8 mA
2.3
1.8
I
OH
=
-
12 mA
2.7
2.2
I
OH
=
-
18 mA
3.0
2.4
I
OH
=
-
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
2.3
-
3.6
0.2
V
I
OL
=
8 mA
2.3
0.6
I
OL
=
12 mA
2.7
0.4
I
OL
=
16 mA
3.0
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
V
I
5.5V
2.3
-
3.6
5.0
A
I
OZ
3-STATE I/O Leakage
0
V
O
5.5V
2.3
-
3.6
5.0
A
V
I
=
V
IH
or V
IL
I
OFF
Power-Off Leakage Current
V
I
or V
O
=
5.5V
0
10
A
5
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7
4
LCX16500
DC Electrical Characteristics
(Continued)
Note 10: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
C to
+
85
C
Units
(V)
Min
Max
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.3
-
3.6
20
A
3.6V
V
I
, V
O
5.5V (Note 10)
2.3
-
3.6
20
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.3
-
3.6
500
A
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
30 pF
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
170
MHz
t
PHL
Propagation Delay
1.5
6.0
1.5
7.0
1.5
7.2
ns
t
PLH
Bus to Bus
1.5
6.0
1.5
7.0
1.5
7.2
t
PHL
Propagation Delay
1.5
6.7
1.5
8.0
1.5
8.4
ns
t
PLH
Clock to Bus
1.5
6.7
1.5
8.0
1.5
8.4
t
PHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PLH
LE to Bus
1.5
7.0
1.5
8.0
1.5
8.4
t
PZL
Output Enable Time
1.5
7.2
1.5
8.2
1.5
9.4
ns
t
PZH
1.5
7.2
1.5
8.2
1.5
9.4
t
PLZ
Output Disable Time
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PHZ
1.5
7.0
1.5
8.0
1.5
8.4
t
S
Setup Time
2.5
2.5
3.0
ns
t
H
Hold Time
1.5
1.5
2.0
ns
t
W
Pulse Width
3.0
3.0
3.5
ns
t
OSHL
Output to Output Skew
1.0
ns
t
OSLH
(Note 11)
1.0
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
-
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
-
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
7
pF
C
I/O
Input/Output Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10 MHz
20
pF