2005 Fairchild Semiconductor Corporation
DS012414
www.fairchildsemi.com
March 1995
Revised February 2005
7
4LCX74 Low
V
o
l
t
age
Dual
D-T
ype
Posi
ti
ve Edg
e
-T
r
i
gger
ed F
l
i
p
-Fl
op wi
th
5V T
o
l
e
ran
t
Input
s
74LCX74
Low Voltage Dual D-Type Positive
Edge-Triggered Flip-Flop with 5V Tolerant Inputs
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and
Q HIGH
Features
s
5V tolerant inputs
s
2.3V3.6V V
CC
specifications provided
s
7.0 ns t
PD
max (V
CC
3.3V), 10
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
r
24 mA output drive (V
CC
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds JEDEC 78 conditions
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
s
Leadless Pb-Free DQFN package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: DQFN package available in Tape and Reel only.
Note 2: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74LCX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74MX_NL
(Note 2)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74BQX
(Note 1)
MLP014A
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX74MTCX_NL
(Note 2)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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2
74L
C
X
74
Logic Symbols
IEEE/IEC
Pin Descriptions
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pad Assignment for DQFN
(Top View)
Truth Table
(Each Half)
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
Previous Q(Q) before LOW-to-HIGH Transition of Clock
Pin Names
Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
Inputs
Outputs
S
D
C
D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
3
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7
4LCX74
Absolute Maximum Ratings
(Note 3)
Recommended Operating Conditions
(Note 4)
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 4: I
O
Absolute Maximum Rating must be observed.
Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
7.0
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to V
CC
0.5
Output in HIGH or LOW State (Note 4)
V
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
50
V
O
!
V
CC
I
O
DC Output Source/Sink Current
r
50
mA
I
CC
DC Supply Current per Supply Pin
r
100
mA
I
GND
DC Ground Current per Ground Pin
r
100
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
I
OH
/I
OL
Output Current
V
CC
3.0V
3.6V
r
24
mA
V
CC
2.7V
3.0V
r
12
V
CC
2.3V
2.7V
r
8
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
40
q
C to
85
q
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3
2.7
1.7
V
2.7
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
2.7
0.7
V
2.3
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
100
P
A
2.3
3.6
V
CC
- 0.2
I
OH
= -8 mA
2.3
1.8
V
I
OH
12 mA
2.7
2.2
I
OH
18 mA
3.0
2.4
I
OH
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
100
P
A
2.3
3.6
0.2
I
OL
= 8mA
2.3
0.6
I
OL
12 mA
2.7
0.4
V
I
OL
16 mA
3.0
0.4
I
OL
24 mA
3.0
0.55
I
I
Input Leakage Current
0
d
V
I
d
5.5V
2.3
3.6
r
5.0
P
A
I
OFF
Power-Off Leakage Current
V
I
or V
O
5.5V
0
10
P
A
I
CC
Quiescent Supply Current
V
I
V
CC
or GND
2.3
3.6
10
P
A
3.6V
d
V
I
d
5.5V
2.3
3.6
r
10
'
I
CC
Increase in I
CC
per Input
V
IH
V
CC
0.6V
2.3
3.6
500
P
A
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4
74L
C
X
74
AC Electrical Characteristics
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
T
A
40
q
C to
85
q
C, R
L
500
:
Units
V
CC
3.3V
r
0.3V
V
CC
2.7V
V
CC
2.5V
r
0.2V
C
L
50 pF
C
L
50 pF
C
L
30 pF
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
150
150
MHz
t
PHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PLH
CP
n
to Q
n
or Q
n
1.5
7.0
1.5
8.0
1.5
8.4
t
PHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PLH
C
Dn
or S
Dn
to Q
n
or Q
n
1.5
7.0
1.5
8.0
1.5
8.4
t
S
Setup Time
2.5
2.5
4.0
ns
t
H
Hold Time
1.5
1.5
2.0
ns
t
W
Pulse Width CP
3.3
3.3
4.0
ns
t
W
Pulse Width and C
D
, S
D
3.3
3.6
4.0
ns
t
REC
Recovery Time
2.5
3.0
4.5
ns
t
OSHL
Output to Output Skew
1.0
ns
t
OSLH
(Note 6)
1.0
Symbol
Parameter
Conditions
V
CC
(V)
T
A
25
q
C
Unit
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.8
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Peak V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.8
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
Open, V
I
0V or V
CC
7
pF
C
OUT
Output Capacitance
V
CC
3.3V, V
I
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
3.3V, V
I
0V or V
CC
, f
10 MHz
25
pF
5
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7
4LCX74
AC Loading and Waveforms
Generic for LCX Family
FIGURE 1. AC Test Circuit
(C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay, Pulse Width and t
rec
Waveforms
3-STATE Output High Enable and
Disable TImes for Logic
3-STATE Output Low Enable and
Disable Times for Logic
Setup Time, Hold TIme and Recovery TIme for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f = 1MHz, t
r
= t
f
= 3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
t
PZH
,t
PHZ
GND
Symbol
V
CC
3.3V
r
0.3V
2.7V
2.5V
r
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
0.3V
V
OL
0.3V
V
OL
0.15V
V
y
V
OH
0.3V
V
OH
0.3V
V
OH
0.15V
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6
74L
C
X
74
Schematic Diagram
Generic for LCX Family
7
www.fairchildsemi.com
7
4LCX74
Tape and Reel Specification
Tape Format for DQFN
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Cavities
Status
Status
Leader (Start End)
125 (typ)
Empty
Sealed
BQX
Carrier
2500/3000
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Tape Size
A
B
C
D
N
W1
W2
12 mm
13.0
0.059
0.512
0.795
7.008
0.488
0.724
(330)
(1.50)
(13.00)
(20.20)
(178)
(12.4)
(18.4)
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8
74L
C
X
74
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
9
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7
4LCX74
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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10
74L
C
X
74
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package Number MLP014A
11
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7
4LCX74 Low
V
o
l
t
age
Dual
D-T
ype
Posi
ti
ve Edg
e
-T
r
i
gger
ed F
l
i
p
-Fl
op wi
th
5V T
o
l
e
ran
t
Input
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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