2005 Fairchild Semiconductor Corporation
DS012025
www.fairchildsemi.com
March 1999
Revised June 2005
7
4
L
V
T1
6240
74L
VTH16240 Low
V
o
l
t
age 16-Bi
t Inve
rti
ng Buff
er/
L
ine Dri
ver wit
h
3-
ST
A
T
E Output
s
74LVT16240 74LVTH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT16240 and LVTH16240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus-oriented
transmitter/receiver. The device is nibble controlled.
Individual 3-STATE control inputs can be shorted together
for 8-bit or 16-bit operation.
The LVTH16240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT16240 and
LVTH16240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16240),
also available without bushold feature (74LVT16240)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 16240
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package
Number
Package Description
74LVT16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74L
VT16240
74L
VTH16240
Connection Diagram
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Functional Description
The LVT16240 and LVTH16240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble
(4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted
together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OE
n
) input for each nib-
ble. When OE
n
is LOW, the outputs are in 2-state mode. When OE
n
is HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
OE
n
Output Enable Inputs (Active LOW)
I
0
I
15
Inputs
O
0
O
15
3-STATE Outputs
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
3
I
8
I
11
O
8
O
11
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
4
I
12
I
15
O
12
O
15
L
L
H
L
H
L
H
X
Z
3
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7
4
L
V
T1
6240
74L
VTH16240
Absolute Maximum Ratings
(Note 1)
Recommended Operating Conditions
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
4.6
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to V
CC
0.5
Output in HIGH or LOW State (Note 2)
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
I
O
DC Output Current
64
V
O
!
V
CC
Output at HIGH State
mA
128
V
O
!
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
r
64
mA
I
GND
DC Ground Current per Ground Pin
r
128
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
32
mA
I
OL
LOW Level Output Current
64
mA
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
(V)
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
(Note 10)
V
IK
Input Clamp Diode Voltage
2.7
1.2
V
I
I
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
d
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
O
t
V
CC
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
0.2
V
I
OH
100
P
A
2.7
2.4
I
OH
8 mA
3.0
2.0
I
OH
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
100
P
A
2.7
0.5
I
OL
24 mA
3.0
0.4
I
OL
16 mA
3.0
0.5
I
OL
32 mA
3.0
0.55
I
OL
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
P
A
V
I
0.8V
(Note 4)
75
V
I
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
P
A
(Note 5)
(Note 4)
Current to Change State
500
(Note 6)
I
I
Input Current
3.6
10
P
A
V
I
5.5V
Control Pins
3.6
r
1
V
I
0V or V
CC
Data Pins
3.6
5
V
I
0V
1
V
I
V
CC
I
OFF
Power Off Leakage Current
0
r
100
P
A
0V
d
V
I
or V
O
d
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5V
r
100
P
A
V
O
0.5V to 3.0V
Output Current
V
I
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.5V
I
OZH
3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.0V
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4
74L
VT16240
74L
VTH16240
DC Electrical Characteristics
(Continued)
Note 3: All typical values are at V
CC
3.3V, T
A
25
q
C.
Note 4: Applies to bushold versions only (LVTH16240).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 8)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output at LOW.
AC Electrical Characteristics
Note 10: All typical values are at V
CC
3.3V, T
A
25
q
C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Note 12: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
(V)
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
(Note 10)
I
OZH
3-STATE Output Leakage Current
3.6
10
P
A
V
CC
V
O
d
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
V
I
GND or V
CC
,
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
V
I
GND or V
CC
,
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
V
I
GND or V
CC
,
Outputs Disabled
I
CCZH
Power Supply Current
3.6
0.19
mA
V
I
GND or V
CC
,
V
CC
d
V
O
d
5.5V,
Outputs Disabled
'
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
0.6V
(Note 7)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
Conditions
(V)
Min
Typ
Max
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 9)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.8
V
(Note 9)
Symbol
Parameter
T
A
40
q
C to
85
q
C, C
L
50 pF, R
L
500
:
Units
V
CC
3.3V
r
0.3V
V
CC
2.7V
Min
Typ
Max
Min
Max
(Note 10)
t
PLH
Propagation Delay Data to Output
1.0
3.5
1.0
4.2
ns
t
PHL
1.0
3.5
1.0
4.0
t
PZH
Output Enable Time
1.0
4.0
1.0
4.9
ns
t
PZL
1.2
4.8
1.2
6.1
t
PHZ
Output Disable Time
1.7
4.7
1.7
5.2
ns
t
PLZ
1.7
4.2
1.7
4.4
t
OSHL
Output to Output Skew
1.0
1.0
ns
t
OSLH
(Note 11)
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
0V, V
I
0V or V
CC
4
pF
C
OUT
Output Capacitance
V
CC
3.0V, V
O
0V or V
CC
8
pF
5
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7
4
L
V
T1
6240
74L
VTH16240
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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