2001 Fairchild Semiconductor Corporation
DS012449
www.fairchildsemi.com
January 2000
Revised October 2001
7
4
L
V
T1
6543
74L
VTH16543 Low
V
o
l
t
age 16-
Bit
Regi
ster
ed T
r
anscei
ver
wit
h
3-ST
A
T
E
Outp
uts
74LVT16543 74LVTH16543
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16543 and LVTH16543 16-bit transceivers
contain two sets of D-type latches for temporary storage of
data flowing in either direction. Separate Latch Enable and
Output Enable inputs are provided for each register to per-
mit independent control of inputting and outputting in either
direction of data flow. Each byte has separate control
inputs, which can be shorted together for full 16-bit opera-
tion.
The LVTH16543 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16543 and
LVTH16543 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16543)
s
Also available without bushold feature (74LVT16543)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
-
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 16543
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74LVT16543MEA
(Preliminary)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16543MTD
(Preliminary)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16543MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74L
VT16543
74L
VTH16543
Connection Diagram
Pin Descriptions
Functional Description
The LVT16543 and LVTH16543 contain two sets of D-type
latches, with separate input and output controls for each.
For data flow from A to B, for example, the A to B Enable
(CEAB) input must be LOW in order to enter data from the
A Port or take data from the B Port as indicated in the Data
I/ O Control Table. With CEAB LOW, a low signal on
(LEAB) input makes the A to B latches transparent; a sub-
sequent LOW-to-HIGH transition of the LEAB line puts the
A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both
LOW, the B output buffers are active and reflect the data
present on the output of the A latches. Control of data flow
from B to A is similar, but using the CEBA, LEBA and
OEBA. Each byte has separate control inputs, allowing the
device to be used as two 8-bit transceivers or as one 16-bit
transceiver.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBA
n
, LEBA
n
and OEBA
n
Pin
Names
Description
OEAB
n
A-to-B Output Enable Input (Active LOW)
OEBA
n
B-to-A Output Enable Input (Active LOW)
CEAB
n
A-to-B Enable Input (Active LOW)
CEBA
n
B-to-A Enable Input (Active LOW)
LEAB
n
A-to-B Latch Enable Input (Active LOW)
LEBA
n
B-to-A Latch Enable Input (Active LOW)
A
0
A
15
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
B
15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
Inputs
Latch Status
(Byte n)
Output
Buffers
(Byte n)
CEAB
n
LEAB
n
OEAB
n
H
X
X
Latched
High Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
High Z
L
X
L
--
Driving
3
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7
4
L
V
T1
6543
74L
VTH16543
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74L
VT16543
74L
VTH16543
Absolute Maximum Ratings
(Note 1)
Recommended Operating Conditions
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: I
O
Absolute Maximum Rating must be observed.
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 2)
V
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
64
mA
I
GND
DC Ground Current per Ground Pin
128
mA
T
STG
Storage Temperature
-
65 to
+
150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH-Level Output Current
-
32
mA
I
OL
LOW-Level Output Current
64
T
A
Free-Air Operating Temperature
-
40
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
5
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4
L
V
T1
6543
74L
VTH16543
DC Electrical Characteristics
Note 3: Applies to bushold versions only (74LVTH16543)
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 7)
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. Output under test held LOW.
Symbol
Parameter
V
CC
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
-
1.2
V
I
I
=
-
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
O
V
CC
-
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
-
0.2
V
I
OH
=
-
100
A
2.7
2.4
V
I
OH
=
-
8 mA
3.0
2.0
V
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
=
100
A
2.7
0.5
V
I
OL
=
24 mA
3.0
0.4
V
I
OL
=
16 mA
3.0
0.5
V
I
OL
=
32 mA
3.0
0.55
V
I
OL
=
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
A
V
I
=
0.8V
(Note 3)
-
75
A
V
I
=
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
A
(Note 4)
(Note 3)
Current to Change State
-
500
A
(Note 5)
I
I
Input Current
3.6
10
A
V
I
=
5.5V
Control Pins
3.6
1
A
V
I
=
0V or V
CC
Data Pins
3.6
-
5
A
V
I
=
0V
1
A
V
I
=
V
CC
I
OFF
Power Off Leakage Current
0
100
A
0V
V
I
or V
O
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5V
100
A
V
O
=
0.5V to 3.0V
Output Current
V
I
=
GND or V
CC
I
OZL
(Note 3)
3-STATE Output Leakage Current
3.6
-
5
A
V
O
=
0.0V
I
OZL
3-STATE Output Leakage Current
3.6
-
5
A
V
O
=
0.5V
I
OZH
(Note 3) 3-STATE Output Leakage Current
3.6
5
A
V
O
=
3.6V
I
OZH
3-STATE Output Leakage Current
3.6
5
A
V
O
=
3.0V
I
OZH
+
3-STATE Output Leakage Current
3.6
10
A
V
CC
<
V
O
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
I
CCZ
+
Power Supply Current
3.6
0.19
mA
V
CC
V
O
5.5V,
Outputs Disabled
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
-
0.6V
(Note 6)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
=
25
C
Units
Conditions
(V)
Min
Typ
Max
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 8)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
-
0.8
V
(Note 8)
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