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Электронный компонент: 74LVTH245MTC

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2005 Fairchild Semiconductor Corporation
DS500203
www.fairchildsemi.com
November 1999
Revised March 2005
7
4
L
V
T2
45
74L
VTH245
Low

V
o
lt
ag
e Oct
a
l
Bi
dir
ecti
onal
T
r
anscei
ver
wit
h
3-
ST
A
T
E
Inp
u
t
s
/Out
put
s
74LVT245 74LVTH245
Low Voltage Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The LVT245 and LVTH245 contain eight non-inverting bidi-
rectional buffers with 3-STATE outputs and are intended for
bus-oriented applications. The Transmit/Receive (T/R)
input determines the direction of data flow through the bidi-
rectional transceiver. Transmit (active-HIGH) enables data
from A ports to B ports; Receive (active-LOW) enables
data from B ports to A ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
The LVTH245 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT245 and LVTH245
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH245),
also available without bushold feature (74LVT245)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink,
32 mA/
64 mA
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74LVT245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT245SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVT245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVT245MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH245WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH245SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVTH245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH245MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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74
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TH245
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
Inputs
Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
3
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74L
VTH245
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
4.6
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to
7.0
Output in HIGH or LOW State (Note 3)
V
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
I
O
DC Output Current
64
V
O
!
V
CC
Output at HIGH State
mA
128
V
O
!
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
r
64
mA
I
GND
DC Ground Current per Ground Pin
r
128
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
High-Level Output Current
32
mA
I
OL
Low-Level Output Current
64
mA
T
A
Free Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
1.2
V
I
I
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
d
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
O
t
V
CC
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
- 0.2
V
I
OH
100
P
A
2.7
2.4
V
I
OH
8 mA
3.0
2.0
V
I
OH
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
100
P
A
2.7
0.5
V
I
OL
24 mA
3.0
0.4
V
I
OL
16 mA
3.0
0.5
V
I
OL
32 mA
3.0
0.55
V
I
OL
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
P
A
V
I
0.8V
(Note 4)
75
P
A
V
I
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
P
A
(Note 5)
(Note 4)
Current to Change State
500
P
A
(Note 6)
I
I
Input Current
3.6
10
P
A
V
I
5.5V
Control Pins
3.6
r
1
P
A
V
I
0V or V
CC
Data Pins
3.6
5
P
A
V
I
0V
1
P
A
V
I
V
CC
I
OFF
Power Off Leakage Current
0
r
100
P
A
0V
d
V
I
or V
O
d
5.5V
I
PU/PD
Power Up/Down
01.5V
r
100
P
A
V
O
0.5V to V
CC
3-STATE Current
V
I
GND to V
CC
I
OZL
3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.5V
I
OZL
(Note 4) 3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.0V
I
OZH
3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.0V
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74
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TH245
DC Electrical Characteristics
(Continued)
Note 4: Applies to Bushold versions only (LVTH245).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 8)
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 11)
Note 11: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
I
OZH
(Note 4) 3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.6V
I
OZH
3-STATE Output Leakage Current
3.6
10
P
A
V
CC
V
O
d
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
I
CCZ
Power Supply Current
3.6
0.19
mA
V
CC
d
V
O
d
5.5V,
Outputs Disabled
'
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
0.6V
(Note 7)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
Conditions
(V)
Min
Typ
Max
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 9)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.8
V
(Note 9)
Symbol
Parameter
T
A
40
q
C to
85
q
C
Units
C
L
50 pF, R
L
500
:
V
CC
3.3V
r
0.3V
V
CC
2.7V
Min
Max
Min
Max
t
PLH
Propagation Delay
1.2
3.6
1.2
4.0
ns
t
PHL
1.2
3.5
1.2
4.0
t
PZH
Output Enable Time
1.3
5.5
1.3
7.1
ns
t
PZL
1.7
5.7
1.7
6.7
t
PHZ
Output Disable
2.0
5.9
2.0
6.5
ns
t
PLZ
2.0
5.0
2.0
5.1
t
OSHL
Output to Output Skew
1.0
1.0
ns
t
OSLH
(Note 10)
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
0V, V
I
0V or V
CC
4
pF
C
I/O
Input/Output Capacitance
V
CC
3.0V, V
O
0V or V
CC
8
pF
5
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74L
VTH245
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
www.fairchildsemi.com
6
74L
VT245

74
L
V
TH245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74L
VTH245
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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8
74L
VT245


7
4
L
V
TH24
5
Low V
o
l
t
age Oct
a
l Bidi
rec
t
i
onal T
r
an
sceive
r
wi
th 3-
S
T
A
T
E
I
nput
s/
Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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