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Электронный компонент: 74LVTH273WM

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2005 Fairchild Semiconductor Corporation
DS500100
www.fairchildsemi.com
July 1999
Revised March 2005
7
4
L
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Low V
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l
t
age Oct
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ip-
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Cl
ear
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before the
positive clock transition, is transferred to the corresponding
flip-flop's output.
The LVTH273 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH273 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 273
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbols
IEEE/IEC
Order Number
Package
Package Description
Number
74LVTH273WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH273SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH273MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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Connection Diagram
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
LOW-to-HIGH Transition
O
o
Previous O
o
before HIGH-to-LOW of CP
Functional Description
The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear
are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig-
nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
CLR
Clear
O
0
O
7
Outputs
Inputs
Outputs
D
n
CP
CLR
O
n
H
H
H
L
H
L
X
H or L
H
O
o
X
X
L
L
3
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Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Note 4: All typical values are at V
CC
3.3V, T
A
25
q
C.
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
4.6
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to
7.0
Output in HIGH or LOW State (Note 3)
V
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
I
O
DC Output Current
64
V
O
!
V
CC
Output at HIGH State
mA
128
V
O
!
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
r
64
mA
I
GND
DC Ground Current per Ground Pin
r
128
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
32
mA
I
OL
LOW Level Output Current
64
mA
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
(V)
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
(Note 4)
V
IK
Input Clamp Diode Voltage
2.7
1.2
V
I
I
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
d
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
O
t
V
CC
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
0.2
V
I
OH
100
P
A
2.7
2.4
I
OH
8 mA
3.0
2.0
I
OH
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
100
P
A
2.7
0.5
I
OL
24 mA
3.0
0.4
I
OL
16 mA
3.0
0.5
I
OL
32 mA
3.0
0.55
I
OL
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
P
A
V
I
0.8V
75
V
I
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
P
A
(Note 5)
Current to Change State
500
(Note 6)
I
I
Input Current
3.6
10
P
A
V
I
5.5V
Control Pins
3.6
r
1
P
A
V
I
0V or V
CC
Data Pins
3.6
5
P
A
V
I
0V
1
P
A
V
I
V
CC
I
OFF
Power Off Leakage Current
0
r
100
P
A
0V
d
V
I
or V
O
d
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
Outputs LOW
'
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
0.6V
(Note 7)
Other Inputs at V
CC
or GND
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DC Electrical Characteristics
(Continued)
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 8)
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note 10: All typical values are at V
CC
3.3V, T
A
25
q
C.
Capacitance
(Note 11)
Note 11: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883B, Method 3012.
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
Units
Conditions
Min
Typ
Max
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 9)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.8
V
(Note 9)
Symbol
Parameter
T
A
40
q
C to
85
q
C
Units
C
L
50 pF, R
L
500
:
V
CC
3.3V
r
0.3V
V
CC
2.7V
Min
Typ
Max
Min
Max
(Note 10)
f
MAX
Maximum Clock Frequency
150
150
MHz
t
PLH
Propagation Delay
1.7
4.9
1.7
5.5
ns
t
PHL
CP to O
n
1.9
4.8
1.9
5.1
t
PHL
Propagation Delay CLR to O
n
1.6
4.8
1.6
5.4
ns
t
W
Pulse Duration
3.3
3.3
ns
t
S
Setup Time
Data HIGH or LOW before CP
2.3
2.7
ns
CLR HIGH before CP
2.3
2.7
t
H
Hold Time
Data HIGH or LOW after CP
0
0
ns
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
0V, V
I
0V or V
CC
3
pF
C
OUT
Output Capacitance
V
CC
3.0V, V
O
0V or V
CC
6
pF
5
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B