Preliminary
2001 Fairchild Semiconductor Corporation
DS500429
www.fairchildsemi.com
February 2001
Revised August 2001
7
4
L
V
TH32
2374
L
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V
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lt
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3-
ST
A
T
E Output
s
an
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25
S
e
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Resi
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(P
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74LVTH322374
Low Voltage 32-Bit D-Type Flip-Flop
with 3-STATE Outputs
and 25
Series Resistors in the Outputs (Preliminary)
General Description
The LVTH322374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 32-bit opera-
tion.
The LVTH322374 is designed with equivalent 25
series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH322374 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These flip-flops are designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH322374 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Power Down high impedance provides glitch-
free bus loading
s
Outputs include equivalent series resistance of 25
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
Order Number
Package Number
Package Description
74LVTH322374GX
(Note 1)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Preliminary
www.fairchildsemi.com
2
74L
VTH322374
Connection Diagram
(Top Thru View)
Pin Descriptions for FBGA
FBGA Pin Assignments
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
O
o
=
Previous O
o
before HIGH-to-LOW of CP
Functional Description
The LVTH322374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs.
The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all
flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi-
vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP
n
) transition. With the
Output Enable (OE
n
) LOW, the contents of the flip-flops are available at the outputs. When OE
n
is HIGH, the outputs go to
the high impedance state. Operation of the OE
n
input does not affect the state of the flip-flops.
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
I
31
Inputs
O
0
O
31
3-STATE Outputs
1
2
3
4
5
6
A
O
1
O
0
OE
1
CP
1
I
0
I
1
B
O
3
O
2
GND
GND
I
2
I
3
C
O
5
O
4
V
CC1
V
CC1
I
4
I
5
D
O
7
O
6
GND
GND
I
6
I
7
E
O
9
O
8
GND
GND
I
8
I
9
F
O
11
O
10
V
CC1
V
CC1
I
10
I
11
G
O
13
O
12
GND
GND
I
12
I
13
H
O
14
O
15
OE
2
CP
2
I
15
I
14
J
O
17
O
16
OE
3
CP
3
I
16
I
17
K
O
19
O
18
GND
GND
I
18
I
19
L
O
21
O
20
V
CC2
V
CC2
I
20
I
21
M
O
23
O
22
GND
GND
I
22
I
23
N
O
25
O
24
GND
GND
I
24
I
25
P
O
27
O
26
V
CC2
V
CC2
I
26
I
27
R
O
29
O
28
GND
GND
I
28
I
29
T
O
30
O
31
OE
4
CP
4
I
31
I
30
Inputs
Outputs
Inputs
Outputs
CP
1
OE
1
I
0
I
7
O
0
O
7
CP
2
OE
2
I
8
I
15
O
8
O
15
L
H
H
L
H
H
L
L
L
L
L
L
L
L
X
O
o
L
L
X
O
o
X
H
X
Z
X
H
X
Z
Inputs
Outputs
Inputs
Outputs
CP
3
OE
3
I
16
I
23
O
16
O
23
CP
4
OE
4
I
24
I
31
O
24
O
31
L
H
H
L
H
H
L
L
L
L
L
L
L
L
X
O
o
L
L
X
O
o
X
H
X
Z
X
H
X
Z
Preliminary
3
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7
4
L
V
TH32
2374
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
V
CC1
is associated with Bytes 1 and 2.
V
CC2
is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
Preliminary
www.fairchildsemi.com
4
74L
VTH322374
Absolute Maximum Ratings
(Note 2)
Recommended Operating Conditions
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
64
mA
I
GND
DC Ground Current per Ground Pin
128
mA
T
STG
Storage Temperature
-
65 to
+
150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
-
32
mA
I
OL
LOW Level Output Current
64
mA
T
A
Free-Air Operating Temperature
-
40
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
-
1.2
V
I
I
=
-
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
O
V
CC
-
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
-
0.2
V
I
OH
=
-
100
A
3.0
2.0
I
OH
=
-
12 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
=
100
A
3.0
0.8
I
OL
=
12 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
A
V
I
=
0.8V
-
75
V
I
=
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
A
(Note 4)
Current to Change State
-
500
(Note 5)
I
I
Input Current
3.6
10
A
V
I
=
5.5V
Control Pins
3.6
1
V
I
=
0V or V
CC
Data Pins
3.6
-
5
V
I
=
0V
1
V
I
=
V
CC
I
OFF
Power Off Leakage Current
0
100
A
0V
V
I
or V
O
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5V
100
A
V
O
=
0.5V to 3.0V
Output Current
V
I
=
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
-
5
A
V
O
=
0.5V
I
OZH
3-STATE Output Leakage Current
3.6
5
A
V
O
=
3.0V
I
OZH
+
3-STATE Output Leakage Current
3.6
10
A
V
CC
<
V
O
5.5V
I
CCH
Power Supply Current
(V
CC1
or V
CC2
)
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
(V
CC1
or V
CC2
)
3.6
5
mA
Outputs LOW
I
CCZ
Power Supply Current
(V
CC1
or V
CC2
)
3.6
0.19
mA
Outputs Disabled
Preliminary
5
www.fairchildsemi.com
7
4
L
V
TH32
2374
DC Electrical Characteristics
(Continued)
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 7)
Note 7: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Capacitance
(Note 9)
Note 9: Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Max
I
CCZ
+
Power Supply Current
(V
CC1
or V
CC2
)
3.6
0.19
mA
V
CC
V
O
5.5V,
Outputs Disabled
I
CC
Increase in Power Supply Current (V
CC1
or V
CC2
)
3.6
0.2
mA
One Input at V
CC
-
0.6V
(Note 6)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
=
25
C
Units
Conditions
(V)
Min
Typ
Max
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 8)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
-
0.8
V
(Note 8)
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, C
L
=
50 pF, R
L
=
500
Units
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
160
160
MHz
t
PHL
Propagation Delay
2.2
4.9
2.2
5.1
ns
t
PLH
CP to O
n
2.0
5.3
2.0
6.2
t
PZL
Output Enable Time
1.8
4.9
1.8
6.0
ns
t
PZH
1.8
5.6
1.8
6.9
t
PLZ
Output Disable Time
2.0
5.0
2.0
5.1
ns
t
PHZ
2.4
5.4
2.4
5.7
t
S
Setup Time
1.8
2.0
ns
t
H
Hold Time
0.8
0.1
ns
t
W
Pulse Width
3.0
3.0
ns
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
OPEN, V
I
=
0V or V
CC
4
pF
C
OUT
Output Capacitance
V
CC
=
3.0V, V
O
=
0V or V
CC
8
pF
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