Preliminary
2001 Fairchild Semiconductor Corporation
DS500411
www.fairchildsemi.com
September 2000
Revised August 2001
7
4
L
V
TH32
952
Low V
o
lt
age
3
2
-Bi
t
Regist
ered T
r
a
n
sceiv
e
r w
i
th 3-
ST
A
T
E O
u
t
put
s
(
P
rel
i
mina
ry)
74LVTH32952
Low Voltage 32-Bit Registered Transceiver
with 3-STATE Outputs (Preliminary)
General Description
The LVTH32952 is a 32-bit registered transceiver. Four
8-bit back to back registers store data flowing in both direc-
tions between two bidirectional buses. Separate clock,
clock enable, and output enable signals are provided for
each register.
The LVTH32952 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The registered transceiver is designed for low voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment.
The LVTH32952 is fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
-
32 mA/
+
64 mA
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Order Number
Package Number
Package Description
74LVTH32952GX
(Note 1)
BGA114A
(Preliminary)
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
Preliminary
www.fairchildsemi.com
2
74L
VTH32952
Connection Diagram
(Top Thru View)
Truth Table
(Note 2)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
Output High Impedance
=
LOW-to-HIGH Transition.
NC
=
No Change (state established by last valid CP)
B
0
=
State established by last valid CP
Note 2: A to B data flow shown; B to A flow control is the same, but uses
OEBA
n
, CPBA
n
and CEB
n
.
Pin Descriptions
Pin Assignments for FBGA
Inputs
Internal Register Output
A
CPAB
n
CEA
n
OEAB
n
Value
B
X
X
H
L
NC
B
0
X
X
H
H
NC
Z
L
L
L
L
L
L
L
H
L
Z
H
L
L
H
H
H
L
H
H
Z
X
L
X
L
NC
B
0
X
H
X
L
NC
B
0
X
L
X
H
NC
Z
X
H
X
H
NC
Z
Pin Names
Description
A
0
A
31
Data Register A Inputs
B-Register 3-STATE Outputs
B
0
B
31
Data Register B Inputs
A-Register 3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
CEA
n
, CEB
n
Clock Enable
OEAB
n
, OEBA
n
Output Enable Inputs
1
2
3
4
5
6
A
A
0
CEA
1
CPAB
1
CPBA
1
CEB
1
B
0
B
A
2
A
1
OEAB
1
OEBA
1
B
1
B
2
C
A
4
A
3
GND
GND
B
3
B
4
D
A
6
A
5
V
CC1
V
CC1
B
5
B
6
E
A
8
A
7
GND
GND
B
7
B
8
F
A
10
A
9
GND
GND
B
9
B
10
G
A
12
A
11
V
CC1
V
CC1
B
11
B
12
H
A
13
A
14
GND
GND
B
14
B
13
J
A
15
CEA
2
CPAB
2
CPBA
2
CEB
2
B
15
K
NC
CPAB
3
OEAB
2
OEBA
2
CPBA
3
NC
L
A
16
CEA
3
OEAB
3
OEBA
3
CEB
3
B
16
M
A
18
A
17
GND
GND
B
17
B
18
N
A
20
A
19
V
CC2
V
CC2
B
19
B
20
P
A
22
A
21
GND
GND
B
21
B
22
R
A
24
A
23
GND
GND
B
23
B
24
T
A
26
A
25
V
CC2
V
CC2
B
25
B
26
U
A
28
A
27
GND
GND
B
27
B
28
V
A
29
A
30
CPAB
4
CPBA
4
B
30
B
29
W
A
31
CEA
4
OEAB
4
OEBA
4
CEB
4
B
31
Preliminary
3
www.fairchildsemi.com
7
4
L
V
TH32
952
Logic Diagram
Byte 1 of 4
n
=
1 for Byte 1, n
=
2 for Byte 2, etc.
Byte 1: A
0
- A
7
, B
0
- B
7
Byte 2: A
8
- A
15
, B
8
- B
15
Byte 3: A
16
- A
23
, B
16
- B
23
Byte 4: A
24
- A
31
, B
24
- B
31
V
CC1
is associated with Bytes 1 and 2
V
CC2
is associated with Bytes 3 and 4
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Preliminary
www.fairchildsemi.com
4
74L
VTH32952
Absolute Maximum Ratings
(Note 3)
Recommended Operating Conditions
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 4)
V
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
64
mA
I
GND
DC Ground Current per Ground Pin
128
mA
T
STG
Storage Temperature
-
65 to
+
150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
-
32
mA
I
OL
LOW Level Output Current
64
T
A
Free-Air Operating Temperature
-
40
+
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
-
1.2
V
I
I
=
-
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
O
V
CC
-
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
-
0.2
V
I
OH
=
-
100
A
2.7
2.4
V
I
OH
=
-
8 mA
3.0
2.0
V
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
=
100
A
2.7
0.5
V
I
OL
=
24 mA
3.0
0.4
V
I
OL
=
16 mA
3.0
0.5
V
I
OL
=
32 mA
3.0
0.55
V
I
OL
=
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
A
V
I
=
0.8V
-
75
A
V
I
=
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
A
(Note 5)
Current to Change State
-
500
A
(Note 6)
I
I
Input Current
3.6
10
A
V
I
=
5.5V
Control Pins
3.6
1
A
V
I
=
0V or V
CC
Data Pins
3.6
-
5
A
V
I
=
0V
1
A
V
I
=
V
CC
I
OFF
Power Off Leakage Current
0
100
A
0V
V
I
or V
O
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5V
100
A
V
O
=
0.5V to 3.0V
Output Current
V
I
=
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
-
5
A
V
O
=
0.0V
I
OZH
3-STATE Output Leakage Current
3.6
5
A
V
O
=
3.6V
I
OZH
+
3-STATE Output Leakage Current
3.6
10
A
V
CC
<
V
O
5.5V
Preliminary
5
www.fairchildsemi.com
7
4
L
V
TH32
952
DC Electrical Characteristics
(Continued)
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 8)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Capacitance
(Note 10)
Note 10: Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Min
Max
I
CCH
Power Supply Current
V
CC1
or V
CC2
3.6
0.19
mA
Outputs High
I
CCL
Power Supply Current
V
CC1
or V
CC2
3.6
5
mA
Outputs Low
I
CCZ
Power Supply Current
V
CC1
or V
CC2
3.6
0.19
mA
Outputs Disabled
I
CCZ
+
Power Supply Current
V
CC1
or V
CC2
3.6
0.19
mA
V
CC
V
O
5.5V,
Outputs Disabled
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
-
0.6V
(Note 7)
V
CC1
or V
CC2
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
=
25
C
Units
Conditions
(V)
Min
Typ
Max
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 9)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
-
0.8
V
(Note 9)
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
Units
C
L
=
50 pF, R
L
=
500
V
CC
=
3.3
0.3V
V
CC
=
2.7V
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
150
MHz
t
PLH
Propagation Delay
1.3
4.4
1.3
4.7
ns
t
PHL
CPBA or CPAB to A or B
1.3
4.8
1.3
5.0
t
PZH
Output Enable Time
1.0
4.3
1.0
4.9
ns
t
PZL
OE to A or B
1.0
4.8
1.0
5.7
t
PHZ
Output Disable Time
2.1
5.7
2.1
6.2
ns
t
PLZ
OE to A or B
2.1
5.1
2.1
5.3
t
W
Pulse Width, CPAB or CPBA HIGH or LOW
3.3
3.3
ns
t
S
Setup Time
A or B before CPAB or CPBA
1.7
2.5
ns
CEA or CEB before CPAB or CPBA
2.0
2.8
t
H
Hold Time
A or B after CPAB or CPBA
0.8
0.0
ns
CEA or CEB after CPAB or CPBA
0.4
0.0
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
OPEN, V
I
=
0V or V
CC
4
pF
C
I/O
Input/Output Capacitance
V
CC
=
3.0V, V
O
=
0V or V
CC
8
pF
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