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Электронный компонент: 74LVX14MTCX_NL

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2005 Fairchild Semiconductor Corporation
DS011603
www.fairchildsemi.com
March 1993
Revised February 2005
7
4
L
VX14
Low V
o
l
t
age
Hex I
nvert
e
r
wit
h
Sch
m
i
t
t
T
r
igge
r I
nput
74LVX14
Low Voltage Hex Inverter with Schmitt Trigger Input
General Description
The LVX14 contains six inverter gates each with a Schmitt
trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free out-
put signals. In addition, they have a greater noise margin
than conventional inverters.
The LVX14 has hysteresis between the positive-going and
negative-going input thresholds (typically 1.0V) which is
determined internally by transistor ratios and is essentially
insensitive to temperature and supply voltage variations.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74LVX14M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX14MX_NL
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX14SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX14MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX14MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Pin Names
Description
I
n
Inputs
O
n
Outputs
Input
Output
A
O
L
H
H
L
3
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L
VX14
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 3)
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
(Note 4)
Note 4: Input t
r
t
f
3ns
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to 7V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
25 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Power Dissipation
180 mW
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
V
t
Positive Threshold
3.0
2.2
2.2
V
V
t
Negative Threshold
3.0
0.9
0.9
V
V
H
Hysteresis
3.0
0.3
1.2
0.3
1.2
V
V
OH
HIGH Level
2.0
1.9
2.0
1.9
I
OH
50
P
A
Output Voltage
3.0
2.9
3.0
2.9
V
V
IN
V
IL
or V
IH
I
OH
50
P
A
3.0
2.58
2.48
I
OH
4 mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
I
OL
50
P
A
Output Voltage
3.0
0.0
0.1
0.1
V
V
IN
V
IL
or V
IH
I
OL
50
P
A
3.0
0.36
0.44
I
OL
4 mA
I
IN
Input Leakage Current
3.6
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
3.6
2.0
20
P
A
V
IN
V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
C
L
(pF)
(V)
Typ
Limit
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.3
0.5
V
50
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.3
0.5
V
50
V
IHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
V
ILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
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AC Electrical Characteristics
Note 5: Parameter guaranteed by design. t
OSLH
|t
PLHm
t
PLHn
|, t
OSHL
|t
PHLm
t
PHLn
|
Capacitance
Note 6: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
C
L
(pF)
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation
2.7
8.7
16.3
1.0
19.5
ns
15
t
PHL
Delay Time
11.2
19.8
1.0
23.0
50
3.3
r
0.3
6.8
10.6
1.0
12.5
15
9.3
14.1
1.0
16.0
50
t
OSLH
Output to Output
2.7
1.5
1.5
ns 50
t
OSHL
Skew (Note 5)
3.3
1.5
1.5
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Min
Typ
Max
Min
Max
C
IN
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation
21
pF
Capacitance (Note 6)
5
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7
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L
VX14
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A