2005 Fairchild Semiconductor Corporation
DS500202
www.fairchildsemi.com
January 1999
Revised June 2005
7
4
L
VX16
1284 Lo
w
V
o
lt
age
I
E
E
E
161284
T
r
anslat
in
g T
r
anscei
ver
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r
14 mA) and are connected to a
separate power supply pin (V
CC
-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V
CC
-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
A
8
/B
1
B
8
transceiver
pins.
Features
s
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s
Translation capability allows outputs on the cable side to
interface with 5V signals
s
All inputs have hysteresis to provide noise margin
s
B and Y output resistance optimized to drive external
cable
s
B and Y outputs in high impedance mode during power
down
s
Inputs and outputs on cable side have internal pull-up
resistors
s
Flow-through pin configuration allows easy interface
between the "Peripheral and Host"
s
Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LVX161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVX161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
HD
High Drive Enable Input (Active HIGH)
DIR
Direction Control Input
A
1
A
8
Inputs or Outputs
B
1
B
8
Inputs or Outputs
A
9
A
13
Inputs
Y
9
Y
13
Outputs
A
14
A
17
Outputs
C
14
C
17
Inputs
PLH
IN
Peripheral Logic HIGH Input
PLH
Peripheral Logic HIGH Output
HLH
IN
Host Logic HIGH Input
HLH
Host Logic HIGH Output
3
www.fairchildsemi.com
7
4
L
VX16
1284
Absolute Maximum Ratings
(Note 3)
Recommended Operating
Conditions
Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Fairchild does not recom-
mend operation outside the databook specifications.
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Supply Voltage
V
CC
0.5V to
4.6V
V
CC--Cable
0.5V to
7.0V
V
CC--Cable
Must Be
t
V
CC
Input Voltage (V
I
)--(Note 4)
A
1
A
13
, PLH
IN
, DIR, HD
0.5V to V
CC
0.5V
B
1
B
8
, C
14
C
17
, HLH
IN
0.5V to
5.5V (DC)
B
1
B
8
, C
14
C
17
, HLH
IN
2.0V to
7.0V*
*40 ns Transient
Output Voltage (V
O
)
A
1
A
8
, A
14
A
17
, HLH
0.5V to V
CC
0.5V
B
1
B
8
, Y
9
Y
13
, PLH
0.5V to
5.5V (DC)
B
1
B
8
, Y
9
Y
13
, PLH
2.0V to
7.0V*
*40 ns Transient
DC Output Current (I
O
)
A
1
A
8
, HLH
r
25 mA
B
1
B
8
, Y
9
Y
13
r
50 mA
PLH (Output LOW)
84 mA
PLH (Output HIGH)
50 mA
Input Diode Current (I
IK
)--(Note 4)
DIR, HD, A
9
A
13
, PLH, HLH, C
14
C
17
20 mA
Output Diode Current (I
OK
)
A
1
A
8
, A
14
A
17
, HLH
r
50 mA
B
1
B
8
, Y
9
Y
13
, PLH
50 mA
DC Continuous V
CC
or Ground
Current
r
200 mA
Storage Temperature
65
q
C to
150
q
C
ESD (HBM) Last Passing Voltage
2000V
Supply Voltage
V
CC
3.0V to 3.6V
V
CC--Cable
3.0V to 5.5V
DC Input Voltage (V
I
)
0V to V
CC
Open Drain Voltage (V
O
)
0V to 5.5V
Operating Temperature (T
A
)
40
q
C to
85
q
C
Symbol
Parameter
V
CC
(V)
V
CC--Cable
(V)
T
A
0
q
C
T
A
40
q
C
Units
Conditions
to
70
q
C
to
85
q
C
Guaranteed Limits
V
IK
Input Clamp
3.0
3.0
1.2
1.2
V
I
i
18 mA
Diode Voltage
V
IH
Minimum
A
n
, B
n
, PLH
IN
, DIR, HD
3.03.6
3.05.5
2.0
2.0
V
HIGH Level
C
n
3.03.6
3.05.5
2.3
2.3
Input Voltage
HLH
IN
3.03.6
3.05.5
2.6
2.6
V
IL
Maximum
A
n
, B
n
, PLH
IN
, DIR, HD
3.03.6
3.05.5
0.8
0.8
V
LOW Level
C
n
3.03.6
3.05.5
0.8
0.8
Input Voltage
HLH
IN
3.03.6
3.05.5
1.6
1.6
'
V
T
Minimum Input
A
n
, B
n
, PLH
IN
, DIR, HD
3.3
5.0
0.4
0.4
V
V
T
V
T
Hysteresis
C
n
3.3
5.0
0.8
0.8
V
T
V
T
HLH
IN
3.3
5.0
0.2
0.2
V
T
V
T
V
OH
Minimum HIGH
A
n
, HLH
3.0
3.0
2.8
2.8
V
I
OH
50
P
A
Level Output
3.0
3.0
2.4
2.4
I
OH
4 mA
Voltage
B
n
, Y
n
3.0
3.0
2.0
2.0
I
OH
14 mA
B
n
, Y
n
3.0
4.5
2.23
2.23
I
OH
14 mA
PLH
3.15
3.15
3.1
3.1
I
OH
500
P
A
www.fairchildsemi.com
4
74L
VX161284
DC Electrical Characteristics
(Continued)
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD
HIGH).
Note 6: Power-down leakage to V
CC
or V
CC--Cable
is tested by simultaneously forcing all pins on the cable-side (B
1
B
8
, Y
9
Y
13
, PLH, C
14
C
17
and HLH
IN
)
to 5.5V and measuring the resulting I
CC
or I
CC--Cable
.
Note 7: This parameter is guaranteed but not tested, characterized only.
Symbol
Parameter
V
CC
(V)
V
CC--Cable
(V)
T
A
0
q
C
T
A
40
q
C
Units
Conditions
to
70
q
C
to
85
q
C
Guaranteed Limits
V
OL
Maximum LOW
A
n
, HLH
3.0
3.0
0.2
0.2
V
I
OL
50
P
A
Level Output
3.0
3.0
0.4
0.4
I
OL
4 mA
Voltage
B
n
, Y
n
3.0
3.0
0.8
0.8
I
OL
14 mA
B
n
, Y
n
3.0
4.5
0.77
0.77
I
OL
14 mA
PLH
3.0
3.0
0.85
0.95
I
OL
84 mA
PLH
3.0
4.5
0.8
0.9
I
OL
84 mA
R
D
Maximum Output
B
1
B
8
, Y
9
Y
13
3.3
3.3
60
60
:
(Note 5)(Note 7)
Impedance
3.3
5.0
55
55
Minimum Output
B
1
B
8
, Y
9
Y
13
3.3
3.3
30
30
(Note 5)(Note 7)
Impedance
3.3
5.0
35
35
R
P
Maximum Pull-Up
B
1
B
8
, Y
9
Y
13,
3.3
3.3
1650
1650
:
Resistance
C
14
C
17
3.3
5.0
1650
1650
Minimum Pull-Up
B
1
B
8
, Y
9
Y
13
3.3
3.3
1150
1150
:
Resistance
C
14
C
17
3.3
5.0
1150
1150
I
IH
Maximum Input
A
9
A
13
, PLH
IN
,
3.6
3.6
1.0
1.0
P
A
V
I
3.6V
Current in
HD, DIR, HLH
IN
HIGH State
C
14
C
17
3.6
3.6
50.0
50.0
V
I
3.6V
C
14
C
17
3.6
5.5
100
100
V
I
5.5V
I
IL
Maximum Input
A
9
A
13
, PLH
IN
,
3.6
3.6
1.0
1.0
P
A
V
I
0.0V
Current in
HD, DIR, HLH
IN
LOW State
C
14
C
17
3.6
3.6
3.5
3.5
mA
V
I
0.0V
C
14
C
17
3.6
5.5
5.0
5.0
mA
V
I
0.0V
I
OZH
Maximum Output
A
1
A
8
3.6
3.6
20
20
P
A
V
O
3.6V
Disable Current
B
1
B
8
3.6
3.6
50
50
P
A
V
O
3.6V
(HIGH)
B
1
B
8
3.6
5.5
100
100
P
A
V
O
5.5V
I
OZL
Maximum
A
1
A
8
3.6
3.6
20
20
P
A
V
O
0.0V
Output Disable
B
1
B
8
3.6
3.6
3.5
3.5
mA
Current (LOW)
B
1
B
8
3.6
5.5
5.0
5.0
mA
I
OFF
Power Down
B
1
B
8
, Y
9
Y
13
,
0.0
0.0
100
100
P
A
V
O
5.5V
Output Leakage
PLH
I
OFF
Power Down
C
14
C
17
, HLH
IN
0.0
0.0
100
100
P
A
V
I
5.5V
Input Leakage
I
OFF--ICC
Power Down
0.0
0.0
250
250
P
A
(Note 6)
Leakage to V
CC
I
OFF--ICC2
Power Down Leakage
0.0
0.0
250
250
P
A
(Note 6)
to V
CC--Cable
I
CC
Maximum Supply
3.6
3.6
45
45
mA
V
I
V
CC
or GND
Current
3.6
5.5
70
70
mA
V
I
V
CC
or GND
5
www.fairchildsemi.com
7
4
L
VX16
1284
AC Electrical Characteristics
Note 8: Open Drain
Note 9: t
SKEW
is measured for common edge output transitions and compares the measured propagation delay for a given path type:
(i) A
1
A
8
to B
1
B
8
, A
9
A
13
to Y
9
Y
13
(ii) B
1
B
8
to A
1
A
8
(iii) C
14
C
17
to A
14
A
17
Note 10: This parameter is guaranteed but not tested, characterized only.
Capacitance
Note 11: C
I/O
is measured at frequency
1 MHz, per MIL-STD-883B, Method 3012
Symbol
Parameter
T
A
0
q
C to
70
q
C
T
A
40
q
C to
85
q
C
Units
Figure
Number
V
CC
3.0V3.6V
V
CC
3.0V3.6V
V
CC--Cable
3.0V5.5V
V
CC--Cable
3.0V5.5V
Min
Max
Min
Max
t
PHL
A
1
A
8
to B
1
B
8
2.0
40.0
2.0
44.0
ns
Figure 1
t
PLH
A
1
A
8
to B
1
B
8
2.0
40.0
2.0
44.0
ns
Figure 2
t
PHL
B
1
B
8
to A
1
A
8
2.0
40.0
2.0
44.0
ns
Figure 3
t
PLH
B
1
B
8
to A
1
A
8
2.0
40.0
2.0
44.0
ns
Figure 3
t
PHL
A
9
A
13
to Y
9
Y
13
2.0
40.0
2.0
44.0
ns
Figure 1
t
PLH
A
9
A
13
to Y
9
Y
13
2.0
40.0
2.0
44.0
ns
Figure 2
t
PHL
C
14
C
17
to A
14
A
17
2.0
40.0
2.0
44.0
ns
Figure 3
t
PLH
C
14
C
17
to A
14
A
17
2.0
40.0
2.0
44.0
ns
Figure 3
t
SKEW
LH-LH or HL-HL
10.0
12.0
ns
(Note 9)
t
PHL
PLH
IN
to PLH
2.0
40.0
2.0
44.0
ns
Figure 1
t
PLH
PLH
IN
to PLH
2.0
40.0
2.0
44.0
ns
Figure 2
t
PHL
HLH
IN
to HLH
2.0
40.0
2.0
44.0
ns
Figure 3
t
PLH
HLH
IN
to HLH
2.0
40.0
2.0
44.0
ns
Figure 3
t
PHZ
Output Disable Time
2.0
15.0
2.0
18.0
ns
Figure 7
t
PLZ
DIR to A
1
A
8
2.0
15.0
2.0
18.0
t
PZH
Output Enable Time
2.0
50.0
2.0
50.0
ns
Figure 8
t
PZL
DIR to A
1
A
8
2.0
50.0
2.0
50.0
t
PHZ
Output Disable Time
2.0
50.0
2.0
50.0
ns
Figure 9
t
PLZ
DIR to B
1
B
8
2.0
50.0
2.0
50.0
t
pEN
Output Enable Time
2.0
25.0
2.0
28.0
ns
Figure 2
HD to B
1
B
8
, Y
9
Y
13
2.0
25.0
2.0
28.0
t
pDIS
Output Disable Time
2.0
25.0
2.0
28.0
ns
Figure 2
HD to B
1
B
8
, Y
9
Y
13
2.0
25.0
2.0
28.0
t
pEN
t
pDIS
Output Enable-
10.0
12.0
ns
Output Disable
t
SLEW
Output Slew Rate
t
PLH
B
1
B
8
, Y
9
Y
13
0.05
0.40
0.05
0.40
V/ns
Figure 5
t
PHL
0.05
0.40
0.05
0.40
Figure 4
t
r
, t
f
t
RISE
and t
FALL
120
120
ns
Figure 6
B
1
B
8
(Note 8),
120
120
(Note 10)
Y
9
Y
13
(Note 8)
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
3
pF
V
CC
0.0V (HD, DIR, A
9
A
13
, C
14
C
17
, PLH
IN
and HLH
IN
)
C
I/O
(Note 11)
I/O Pin Capacitance
5
pF
V
CC
3.3V
PDF 
ZIP