2005 Fairchild Semiconductor Corporation
DS011613
www.fairchildsemi.com
June 1993
Revised April 2005
7
4
L
VX37
3
Low V
o
l
t
age Oct
a
l T
r
an
sp
ar
ent Lat
ch
wi
th 3-ST
A
T
E
Out
put
s
74LVX373
Low Voltage Octal Transparent Latch with
3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is LOW, the data satisfying the input timing
requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state. The inputs tolerate
up to 7V allowing interface of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
Z
High Impedance
X
Immaterial
O
0
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Order Number
Package Number
Package Description
74LVX373M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX373SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
O
0
O
7
3-STATE Latch Outputs
Inputs
Outputs
LE
OE
D
n
O
n
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
0
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74
L
VX373
Functional Description
The LVX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
(Note 3)
Note 3: Input t
r
t
f
3 ns.
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to 7V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
25 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
r
75 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Power Dissipation
180 mW
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Input Rise and Fall Time (
'
t/
'
V)
0 ns/V to 100 ns/V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.5
1.5
Input Voltage
3.0
2.0
2.0
V
3.6
2.4
2.4
V
IL
LOW Level
2.0
0.5
0.5
Input Voltage
3.0
0.8
0.8
V
3.6
0.8
0.8
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
IN
V
IH
or V
IL
I
OH
50
P
A
Output Voltage
3.0
2.9
3.0
2.9
V
I
OH
50
P
A
3.0
2.58
2.48
I
OH
4 mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
V
IN
V
IH
or V
IL
I
OL
50
P
A
Output Voltage
3.0
0.0
0.1
0.1
V
I
OL
50
P
A
3.0
0.36
0.44
I
OL
4 mA
I
OZ
3-STATE Output
3.6
r
0.25
r
2.5
P
A
V
IN
V
IH
or V
IL
Off-State Current
V
OUT
V
CC
or GND
I
IN
Input Leakage Current
3.6
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
3.6
4.0
40.0
P
A
V
IN
V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
C
L
(pF)
(V)
Typ
Limit
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.5
0.8
V
50
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.5
0.8
V
50
V
IHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
V
ILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
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VX373
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
OSLH
|t
PLHm
t
PLHn
|, t
OSHL
|t
PHLm
t
PHLn
|
Capacitance
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay Time
2.7
7.7
15.0
1.0
18.5
ns
C
L
15 pF
t
PHL
D
n
to O
n
10.2
18.5
1.0
22.0
C
L
50 pF
3.3
r
0.3
6.0
9.7
1.0
11.5
C
L
15 pF
8.5
13.2
1.0
15.0
C
L
50 pF
t
PLH
Propagation Delay Time
2.7
7.5
14.5
1.0
17.5
ns
C
L
15 pF
t
PHL
LE to O
n
10.0
18.0
1.0
21.0
C
L
50 pF
3.3
r
0.3
5.8
9.3
1.0
11.0
C
L
15 pF
8.3
12.8
1.0
14.5
C
L
50 pF
t
PZL
3-STATE Output
2.7
7.7
15.0
1.0
18.5
ns
C
L
15 pF, R
L
1 k
:
t
PZH
Enable Time
10.2
18.5
1.0
22.0
C
L
50 pF, R
L
1 k
:
3.3
r
0.3
6.0
9.7
1.0
11.5
C
L
15 pF, R
L
1 k
:
8.5
13.2
1.0
15.0
C
L
50 pF, R
L
1 k
:
t
PLZ
3-STATE Output
2.7
9.8
18.0
1.0
21.0
ns
C
L
50 pF, R
L
1 k
:
t
PHZ
Disable Time
3.3
r
0.3
8.2
12.8
1.0
14.5
C
L
50 pF, R
L
1 k
:
t
W
LE Pulse Width, HIGH
2.7
6.5
7.5
ns
3.3
r
0.3
5.0
5.0
t
S
Setup Time, D
n
to LE
2.7
6.0
6.0
ns
3.3
r
0.3
4.0
4.0
t
H
Hold Time, D
n
to LE
2.7
1.0
1.0
ns
3.3
r
0.3
1.0
1.0
t
OSLH
Output to Output Skew
2.7
1.5
1.5
ns
C
L
50 pF
t
OSHL
(Note 4)
3.3
1.5
1.5
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Min
Typ
Max
Min
Max
C
IN
Input Capacitance
4
10
10
pF
C
OUT
Output Capacitance
6
pF
C
PD
Power Dissipation
27
pF
Capacitance (Note 5)
5
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74
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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