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Электронный компонент: 74LVX74

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2005 Fairchild Semiconductor Corporation
DS011606
www.fairchildsemi.com
May 1993
Revised February 2005
7
4
L
VX74
Low V
o
l
t
age
Dual
D-T
ype
Posit
i
ve Edge-
T
r
i
gger
ed Fl
ip-
F
l
o
p
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
s
Input voltage level translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Order Number
Package
Package Description
Number
74LVX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX74MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names
Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
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2
74
L
V
X
7
4
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
Previous Q(Q) before LOW-to-HIGH Transition of Clock
Inputs
Outputs
S
D
C
D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
3
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7
4
L
VX74
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 3)
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
(Note 4)
Note 4: Input t
r
t
f
3 ns
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to 7V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
25 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Power Dissipation
180 mW
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Input Rise and Fall Time (
'
t/
'
V)
0 ns/V to 100 ns/V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.5
1.5
Input Voltage
3.0
2.0
2.0
V
3.6
2.4
2.4
V
IL
LOW Level
2.0
0.5
0.5
Input Voltage
3.0
0.8
0.8
V
3.6
0.8
0.8
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
IN
V
IL
or V
IH
I
OH
50
P
A
Output Voltage
3.0
2.9
3.0
2.9
V
I
OH
50
P
A
3.0
2.58
2.48
I
OH
4 mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
V
IN
V
IL
or V
IH
I
OL
50
P
A
Output Voltage
3.0
0.0
0.1
0.1
V
I
OL
50
P
A
3.0
0.36
0.44
I
OL
4 mA
I
IN
Input Leakage Current
3.6
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
3.6
2.0
20.0
P
A
V
IN
V
CC
or GND
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
Units
C
L
(pF)
Typ
Limit
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.3
0.5
V
50
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.3
0.5
V
50
V
IHD
Minimum High Level Dynamic Input Voltage
3.3
2.0
V
50
V
ILD
Maximum Low Level Dynamic Input Voltage
3.3
0.8
V
50
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4
74
L
V
X
7
4
AC Electrical Characteristics
Note 5: Parameter guaranteed by design. t
OSLH
|t
PLHm
t
PLHn
|, t
OSLH
|t
PHLm
t
PHLn
|
Capacitance
Note 6: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
C
L
(pF)
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
2.7
7.3
15
1.0
18.5
ns
15
t
PHL
CP
n
to Q
n
or Q
n
9.8
18.5
1.0
22 50
3.3
r
0.3
5.7
9.7
1.0
11.5
15
8.2
13.2
1.0
15
50
t
PLH
Propagation Delay
2.7
8.4
15.6
1.0
18.5
ns
15
t
PHL
C
Dn
to S
Dn
to Q
n
or Q
n
10.9
19.1
1.0
22 50
3.3
r
0.3
6.6
10.1
1.0
12
15
9.1
13.6
1.0
15.5
50
t
W
CP
n
or C
Dn
or S
Dn
2.7
8.5
10
ns
Pulse Width
3.3
r
0.3
6
7
t
S
Setup Time
2.7
8.0
9.5
ns
D
n
to CP
n
3.3
r
0.3
5.5
6.5
t
H
Hold Time
2.7
0.5
0.5
ns
D
n
to CP
n
3.3
r
0.3
0.5
0.5
t
REC
Recovery Time
2.7
6.5
7.5
ns
CP
n
or S
Dn
to CP
n
3.3
r
0.3
5.0
5.0
f
MAX
Maximum Clock Frequency
2.7
55
135
50
MHz
15
45
60
40
50
3.3
r
0.3
95
145
80
15
60
85
50
50
t
OSLH
Output to Output Skew
2.7
1.5
1.5
ns
50
t
OSHL
(Note 5)
3.3
1.5
1.5
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Min
Typ
Max
Min
Max
C
IN
Input Capacitance
4
10
10
pF
C
PD
Power Dissipation
25
pF
Capacitance (Note 6)
5
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7
4
L
VX74
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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6
74
L
V
X
7
4
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7
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7
4
L
VX74
Low V
o
l
t
age
Dual
D-T
ype
Posit
i
ve Edge-
T
r
i
gger
ed Fl
ip-
F
l
o
p
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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