2002 Fairchild Semiconductor Corporation
DS500729
www.fairchildsemi.com
May 2002
Revised May 2002
7
4
L
VXZ16
1284
L
o
w
V
o
lt
age IEEE
1
61284 T
r
ansl
ati
ng T
r
ansce
iver
wi
th Pow
e
r-Up Prot
ect
ion
74LVXZ161284
Low Voltage IEEE 161284 Translating Transceiver
with Power-Up Protection
General Description
The LVXZ161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
14 mA) and are connected to a
separate power supply pin (V
CC-Cable
) that allows these
outputs to be driven by a higher supply voltage than
the A-side. The pull-up and pull-down series termination
resistance of these outputs on the cable side is optimized
to drive an external cable. In addition, the C inputs and the
B and Y outputs on the cable side contain internal pull-up
resistors connected to the V
CC-Cable
supply to provide
proper input termination and pull-ups for open drain output
mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
A
8
/B
1
B
8
transceiver
pins.
This device also has an added power-up protection feature
which forces the Y outputs (Y
9
- Y
13
) to a high state after
power-on until one of the associated inputs (A
9
- A
13
) goes
HIGH. When an associated input (A
9
- A
13
) goes HIGH, all
Y outputs (Y
9
- Y
13
) are activated.
Features
I
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
I
Translation capability allows outputs on the cable side to
interface with 5V signals
I
All inputs have hysteresis to provide noise margin
I
B and Y output resistance optimized to drive external
cable
I
B and Y outputs in high impedance mode during power
down
I
C inputs and B, Y outputs on cable side have internal 1.4
k
pull-up resistors
I
Flow-through pin configuration allows easy interface
between the "Peripheral and Host"
I
Replaces the function of two (2) 74ACT1284 devices
I
Power-up protection prevents errors when the printer is
powered on but no valid signal is at the input pins
(A
9
- A
13
).
Ordering Code
Order Number
Package
Number
Package Description
74LVXZ161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LVXZ161284MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LVXZ161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LVXZ161284MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
5
www.fairchildsemi.com
7
4
L
VXZ16
1284
DC Electrical Characteristics
(Continued)
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD
=
HIGH).
Note 6: Power-down leakage to V
CC
or V
CC--Cable
is tested by simultaneously forcing all pins on the cable-side (B
1
B
8
, Y
9
Y
13
, PLH, C
14
C
17
and HLH
IN
)
to 5.5V and measuring the resulting I
CC
or I
CC--Cable
.
Note 7: This parameter is guaranteed but not tested, characterized only.
Note 8: Connect all V
CC
pins and V
CC-Cable
pins when forcing voltage applied, DIR
=
HD
=
0V.
Symbol
Parameter
V
CC
(V)
V
CC--Cable
(V)
T
A
=
0
C
T
A
=
-
40
C
Units
Conditions
to
+
70
C
to
+
85
C
Guaranteed Limits
V
OL
Maximum LOW
A
n
, HLH
3.0
3.0
0.2
0.2
V
I
OL
=
50
A
Level Output
3.0
3.0
0.4
0.4
I
OL
=
4 mA
Voltage
B
n
, Y
n
3.0
3.0
0.8
0.8
I
OL
=
14 mA
B
n
, Y
n
3.0
4.5
0.77
0.77
I
OL
=
14 mA
PLH
3.0
3.0
0.85
0.95
I
OL
=
84 mA
PLH
3.0
4.5
0.8
0.9
I
OL
=
84 mA
R
D
Maximum Output
B
1
- B
8
, Y
9
-Y
13
3.3
3.3
60
60
(Note 5)(Note 7)
Impedance
3.3
5.0
55
55
Minimum Output
B
1
- B
8
, Y
9
- Y
13
3.3
3.3
30
30
(Note 5)(Note 7)
Impedance
3.3
5.0
35
35
R
P
Maximum Pull-Up
B
1
- B
8
, Y
9
- Y
13,
3.3
3.3
1650
1650
Resistance
C
14
- C
17
3.3
5.0
1650
1650
Minimum Pull-Up
B
1
-B
8
, Y
9
- Y
13
3.3
3.3
1150
1150
Resistance
C
14
- C
17
3.3
5.0
1150
1150
I
IH
Maximum Input
A
9
- A
13
, PLH
IN
,
3.6
3.6
1.0
1.0
A
V
I
=
3.6V
Current in
HD, DIR, HLH
IN
HIGH State
C
14
- C
17
3.6
3.6
50.0
50.0
V
I
=
3.6V
C
14
-C
17
3.6
5.5
100
100
V
I
=
5.5V
I
IL
Maximum Input
A
9
- A
13
, PLH
IN
,
3.6
3.6
-
1.0
-
1.0
A
V
I
=
0.0V
Current in
HD, DIR, HLH
IN
LOW State
C
14
- C
17
3.6
3.6
-
3.5
-
3.5
mA
V
I
=
0.0V
C
14
- C
17
3.6
5.5
-
5.0
-
5.0
I
OZH
Maximum Output
A
1
- A
8
3.6
3.6
20
20
A
V
O
=
3.6V
Disable Current
B
1
- B
8
3.6
3.6
50
50
V
O
=
3.6V
(HIGH)
B
1
- B
8
3.6
5.5
100
100
V
O
=
5.5V
I
OZL
Maximum
A
1
- A
8
3.6
3.6
-
20
-
20
A
V
O
=
0.0V
Output Disable
B
1
- B
8
3.6
3.6
-
3.5
-
3.5
mA
Current (LOW)
B
1
- B
8
3.6
5.5
-
5.0
-
5.0
I
OZPU
Maximum Power-Up
Y
9
- Y
13
0 to 1.5
0 to 1.5
350
350
A
V
O
=
5.5V
Disable Current
B
1
- B
8
(Note 8)
(Note 8)
-
5
-
5
mA
V
O
=
0.0V
I
OZPD
Maximum Power-Down Y
9
- Y
13
0 to 1.5
0 to 1.5
350
350
A
V
O
=
5.5V
Disable Current
B
1
- B
8
(Note 8)
(Note 8)
-
5
-
5
mA
V
O
=
0.0V
I
OFF
Power Down
B
1
- B
8
, Y
9
- Y
13
,
0.0
0.0
100
100
A
V
O
=
5.5V
Output Leakage
PLH
I
OFF
Power Down
C
14
C
17
, HLH
IN
0.0
0.0
100
100
A
V
I
=
5.5V
Input Leakage
I
OFF--ICC
Power Down
0.0
0.0
250
250
A
(Note 6)
Leakage to V
CC
I
OFF--ICC2
Power Down Leakage
0.0
0.0
250
250
A
(Note 6)
to V
CC--Cable
I
CC
Maximum Supply
3.6
3.6
45
45
mA
V
I
=
V
CC
or GND
Current
3.6
5.5
70
70
mA
V
I
=
V
CC
or GND