2002 Fairchild Semiconductor Corporation
DS500402
www.fairchildsemi.com
December 2000
Revised November 2002
7
4
VC
X32
374 Lo
w
V
o
lt
age 3
2
-Bi
t
D-T
y
pe
Fli
p
-Fl
ops
wit
h
3.
6V T
o
l
e
ran
t
Input
s a
nd Out
puts
74VCX32374
Low Voltage 32-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32374 contains thirty-two non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 32-bit opera-
tion.
The 74VCX32374 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX32374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.2V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.0 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
24 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering code "G" indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package Number
Package Descriptions
74VCX32374G
(Note 2)(Note 3)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
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2
74VCX32374
Connection Diagram
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
O
0
=
Previous O
0
before HIGH-to-LOW of CP
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
CP
n
Clock Pulse Input
I
0
I
31
Inputs
O
0
O
31
Outputs
1
2
3
4
5
6
A
O
1
O
0
OE
1
CP
1
I
0
I
1
B
O
3
O
2
GND
GND
I
2
I
3
C
O
5
O
4
V
CC
V
CC
I
4
I
5
D
O
7
O
6
GND
GND
I
6
I
7
E
O
9
O
8
GND
GND
I
8
I
9
F
O
11
O
10
V
CC
V
CC
I
10
I
11
G
O
13
O
12
GND
GND
I
12
I
13
H
O
14
O
15
OE
2
CP
2
I
15
I
14
J
O
17
O
16
OE
3
CP
3
I
16
I
17
K
O
19
O
18
GND
GND
I
18
I
19
L
O
21
O
20
V
CC
V
CC
I
20
I
21
M
O
23
O
22
GND
GND
I
22
I
23
N
O
25
O
24
GND
GND
I
24
I
25
P
O
27
O
26
V
CC
V
CC
I
26
I
27
R
O
29
O
28
GND
GND
I
28
I
29
T
O
30
O
31
OE
4
CP
4
I
31
I
30
Inputs
Outputs
Inputs
Outputs
CP
1
OE
1
I
0
I
7
O
0
O
7
CP
2
OE
2
I
8
I
15
O
8
O
15
L
H
H
L
H
H
L
L
L
L
L
L
L
L
X
O
0
L
L
X
O
0
X
H
X
Z
X
H
X
Z
Inputs
Outputs
Inputs
Outputs
CP
3
OE
3
I
16
I
23
O
16
O
23
CP
4
OE
4
I
24
I
31
O
24
O
31
L
H
H
L
H
H
L
L
L
L
L
L
L
L
X
O
0
L
L
X
O
0
X
H
X
Z
X
H
X
Z
3
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7
4
VC
X32
374
Functional Description
The 74VCX32374 consists of thirty-two edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 32-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CP
n
) transition. With the Output
Enable (OE
n
) LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the high impedance state. Operations of the OE
n
input
does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74VCX32374
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
(Note 6)
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 5: I
O
Absolute Maximum Rating must be observed.
Note 6: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to
+
4.6V
Output Voltage (V
O
)
Outputs 3-STATED
-
0.5V to
+
4.6V
Outputs Active (Note 5)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
) V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
V
O
>
V
CC
+
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating 1.2V
to
3.6V
Input Voltage
-
0.3V to
+
3.6V
Output Voltage (V
O
)
Output in Active States
0V to V
CC
Output in 3-STATE
0.0V to 3.6V
Output Current in I
OH
/I
OL
V
CC
=
3.0V to 3.6V
24 mA
V
CC
=
2.3V to 2.7V
18 mA
V
CC
=
1.65V to 2.3V
6 mA
V
CC
=
1.4V to 1.6V
2 mA
V
CC
=
1.2V
100
A
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
2.7 - 3.6
2.0
V
2.3 - 2.7
1.6
1.65 - 2.3
0.65 x V
CC
1.4 - 1.6
0.65 x V
CC
1.2
0.65 x V
CC
V
IL
LOW Level Input Voltage
2.7 - 3.6
0.8
V
2.3 - 2.7
0.7
1.65 - 2.3
0.35 x V
CC
1.4 - 1.6
0.35 x V
CC
1.2
0.05 x V
CC
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
2.7 - 3.6
V
CC
- 0.2
V
I
OH
=
-
12 mA
2.7
2.2
I
OH
=
-
18 mA
3.0
2.4
I
OH
=
-
24 mA
3.0
2.2
I
OH
=
-
100
A
2.3 - 2.7
V
CC
- 0.2
I
OH
=
-
6 mA
2.3
2.0
I
OH
=
-
12 mA
2.3
1.8
I
OH
=
-
18 mA
2.3
1.7
I
OH
=
-
100
A
1.65 - 2.3
V
CC
- 0.2
I
OH
=
-
6 mA
1.65
1.25
I
OH
=
-
100
A
1.4 - 1.6
V
CC
- 0.2
I
OH
=
-
2 mA
1.4
1.05
I
OH
=
-
100
A
1.2
V
CC
- 0.2
5
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7
4
VC
X32
374
DC Electrical Characteristics
(Continued)
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
(Note 8)
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
OL
LOW Level Output Voltage
I
OL
=
100
A 2.7
-
3.6
0.2
V
I
OL
=
12 mA
2.7
0.4
I
OL
=
18 mA
3.0
0.4
I
OL
=
24 mA
3.0
0.55
I
OL
=
100
A
2.7 - 2.7
0.2
I
OL
=
12 mA
2.3
0.4
I
OL
=
18 mA
2.3
0.6
I
OL
=
100
A
1.65 - 2.3
0.2
I
OL
=
6 mA
1.65
0.3
I
OL
=
100
A
1.4 - 1.6
0.2
I
OL
=
2 mA
1.4
0.35
I
OL
=
100
A
1.2
0.05
I
I
Input Leakage Current
0
V
I
3.6V
1.2 - 3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
1.2 - 3.6
10
A
V
I
=
V
IH
or V
IL
I
OFF
Power-OFF Leakage Current
0
(V
I
, V
O
)
3.6V
0
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
1.2 - 3.6
40
A
V
CC
(V
I
, V
O
)
3.6V (Note 7)
1.2 - 3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.7 - 3.6
750
A
Symbol
Parameter
Conditions
V
CC
T
A
=
-
40
C to
+
85
C
Units
Figure
(V)
Min
Max
Number
f
MAX
Maximum Clock Frequency
C
L
=
30 pF, R
L
=
500
3.3
0.3
250
MHz
Setup Time
2.5
0.2
200
1.8
0.15
100
C
L
=
15 pF, R
L
=
2k
1.5
0.1
80
1.2
40
t
PHL
, Propagation
Delay
C
L
=
30 pF, R
L
=
500
3.3
0.3
0.8
3.0
ns
Figures
1, 2
t
PLH
2.5
0.2
1.0
3.9
1.8
0.15
1.5
7.8
C
L
=
15 pF, R
L
=
2k
1.5
0.1
1.0
15.6
Figures
7, 8
1.2
1.5
39
t
PZL
,
Output Enable Time
C
L
=
30 pF, R
L
=
500
3.3
0.3
0.8
3.5
ns
Figures
1, 3, 4
t
PZH
2.5
0.2
1.0
4.6
1.8
0.15
1.5
9.2
C
L
=
15 pF, R
L
=
2k
1.5
0.1
1.0
18.4
Figures
7, 9, 10
1.2
1.5
46
t
PLZ
,
Output Disable Time
C
L
=
30 pF, R
L
=
500
3.3
0.3
0.8
3.5
ns
Figures
1, 3, 4
t
PHZ
2.5
0.2
1.0
3.8
1.8
0.15
1.5
6.8
C
L
=
15 pF, R
L
=
2k
1.5
0.1
1.0
13.6
Figures
7, 9, 10
1.2
1.5
34
t
S
Setup Time
C
L
=
30 pF, R
L
=
500
3.3
0.3
1.5
ns
Figures
1, 6
2.5
0.2
1.5
1.8
0.15
2.5
C
L
=
15 pF, R
L
=
500
1.5
0.1
3
Figures
6, 7
1.2
6
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