August 1998
Revised April 1999
7
4
VC
XR162
601
Lo
w
V
o
lt
age
1
8
-Bi
t
Univer
sal Bus T
r
ansce
iver
s
wi
th 3.6V T
o
ler
ant
I
nputs and O
u
tput
s
and
26
Ser
i
es
Resi
stor
s i
n
the
Output
s
1999 Fairchild Semiconductor Corporation
DS500171.prf
www.fairchildsemi.com
74VCXR162601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs and 26
Series Resistors in
the Outputs
General Description
The VCXR162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCXR162601 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The VCXR162601 is also designed with 26
series resis-
tors on both the A and B Port outputs. This design reduces
line noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
Features
s
1.653.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
26
series resistors on both the A and B Port outputs.
s
t
PD
(A to B, B to A)
3.8 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
s
Power-down HIGH impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
12 mA @ 3.0V V
CC
8 mA @ 2.3V V
CC
3
mA @
1.65V
V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latchup performance exceeds 300 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
74VCXR162601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com
2
74VCXR162601
Connection Diagram
Pin Descriptions
Function Table
(Note 2)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
HIGH Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 3: Output level before the indicated steady-state input conditions
were established
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Logic Diagram
Pin Names
Description
OEAB, OEBA
Output Enable Inputs (Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A
1
A
18
Side A Inputs or 3-STATE Outputs
B
1
B
18
Side B Inputs or 3-STATE Outputs
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
A
n
B
n
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B
0
(Note 3)
H
L
L
X
X
B
0
(Note 3)
L
L
L
L
L
L
L
L
H
H
L
L
L
L
X
B
0
(Note 3)
L
L
L
H
X
B
0
(Note 4)
3
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7
4
VC
XR162
601
Absolute Maximum Ratings
(Note 5)
Recommended Operating
Conditions
(Note 7)
Note 5: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 6: I
O
Absolute Maximum Rating must be observed.
Note 7: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics (2.7V
<
V
CC
3.6V)
Note 8: Outputs disabled or 3-STATE only.
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to
+
4.6V
Output Voltage (V
O
)
Outputs 3-STATE
-
0.5V to
+
4.6V
Outputs Active (Note 6)
-
0.5 to V
CC
+
0.5V
DC Input Diode Current (I
IK
) V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
V
O
>
V
CC
+
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or Ground Current per
Supply Pin (I
CC
or Ground)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Data Retention Only
1.2V to 3.6V
Input Voltage
-
0.3V to 3.6V
Output Voltage (V
O
)
Output in Active States
0V to V
CC
Output in 3-STATE
0.0V to 3.6V
Output Current in I
OH
/I
OL
V
CC
=
3.0V to 3.6V
12 mA
V
CC
=
2.3V to 2.7V
8 mA
V
CC
=
1.65V to 2.3V
3 mA
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
2.73.6
2.0
V
V
IL
LOW Level Input Voltage
2.73.6
0.8
V
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
2.73.6
V
CC
-
0.2
I
OH
=
-
6 mA
2.7
2.2
V
I
OH
=
-
8 mA
3.0
2.4
I
OH
=
-
12 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
2.73.6
0.2
I
OL
=
6 mA
2.7
0.4
V
I
OL
=
8 mA
3.0
0.55
I
OL
=
12 mA
3.0
0.8
I
I
Input Leakage Current
0V
V
I
3.6V
2.73.6
5.0
A
I
OZ
3-STATE Output Leakage
0V
V
O
3.6V
2.73.6
10
A
V
I
=
V
IH
or V
IL
I
OFF
Power Off Leakage Current
0V
(V
I
, V
O
)
3.6V
0
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.73.6
20
A
V
CC
(V
I
, V
O
)
3.6V (Note 8)
2.73.6
20
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.73.6
750
A
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4
74VCXR162601
DC Electrical Characteristics (2.3V
V
CC
2.7V)
Note 9: Outputs disabled or 3-STATE only.
DC Electrical Characteristics (1.65V
V
CC
<
2.3V)
Note 10: Outputs disabled or 3-STATE only.
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
2.32.7
1.6
V
V
IL
LOW Level Input Voltage
2.32.7
0.7
V
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
2.32.7
V
CC
-
0.2
V
I
OH
=
-
4 mA
2.3
2.0
I
OH
=
-
6 mA
2.3
1.8
I
OH
=
-
8 mA
2.3
1.7
V
OL
LOW Level Output Voltage
I
OL
=
100
A
2.32.7
0.2
I
OL
=
6 mA
2.3
0.4
V
I
OL
=
8 mA
2.3
0.6
I
I
Input Leakage Current
0
V
I
3.6V
2.32.7
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
2.32.7
10
A
V
I
=
V
IH
or V
IL
I
OFF
Power Off Leakage Current
0
(V
I
, V
O
)
3.6V
0
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.32.7
20
A
V
CC
(V
I
, V
O
)
3.6V (Note 9)
2.32.7
20
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 2.3
0.65
V
CC
V
V
IL
LOW Level Input Voltage
1.65 - 2.3
0.35
V
CC
V
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 2.3
V
CC
-
0.2
V
I
OH
=
-
3 mA
1.65
1.25
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 2.3
0.2
V
I
OL
=
3 mA
1.65
0.3
I
I
Input Leakage Current
0
V
I
3.6V
1.65 - 2.3
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
1.65 - 2.3
10
A
V
I
=
V
IH
or V
IL
I
OFF
Power Off Leakage Current
0
(V
I
, V
O
)
3.6V
0
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
1.65 - 2.3
20
A
V
CC
(V
I
, V
O
)
3.6V (Note 10)
1.65 - 2.3
20
5
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7
4
VC
XR162
601
AC Electrical Characteristics
(Note 11)
Note 11: For C
L
=
50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, C
L
=
30 pF, R
L
=
500
Units
V
CC
=
3.3V
0.3V
V
CC
=
2.5
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
250
200
125
MHz
t
PHL
, t
PLH
Propagation Delay
A to B or B to A
0.6
3.8
0.8
4.6
1.5
9.2
ns
t
PHL
, t
PLH
Propagation Delay
Clock to A or B
0.6
4.4
0.8
5.5
1.5
9.8
ns
t
PHL
, t
PLH
Propagation Delay
LEBA or LEAB to A or B
0.6
4.4
0.8
5.8
1.5
9.8
ns
t
PZL
, t
PZH
Output Enable Time
OEBA or OEAB to A or B
0.6
4.3
0.8
5.9
1.5
9.8
ns
t
PLZ
, t
PHZ
Output Disable Time
OEBA or OEAB to A or B
0.6
4.3
0.8
4.9
1.5
8.8
ns
t
S
Setup Time
1.5
1.5
2.5
ns
t
H
Hold Time
1.0
1.0
1.0
ns
t
W
Pulse Width
1.5
1.5
4.0
ns
t
OSHL,
t
OSLH
Output to Output Skew (Note 12)
0.5
0.5
0.75
ns
Symbol
Parameter
Conditions
V
CC
(V)
T
A
=
+
25
C
Units
Typical
V
OLP
Quiet Output Dynamic
Peak V
OL
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
1.8
2.5
3.3
0.15
0.25
0.35
V
V
OLV
Quiet Output Dynamic
Valley V
OL
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
1.8
2.5
3.3
0.15
-
0.25
-
0.35
V
V
OHV
Quiet Output Dynamic
Valley V
OH
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
1.8
2.5
3.3
1.5
2.05
2.65
V
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
C
IN
Input Capacitance
V
CC
=
1.8V, 2.5V, or 3.3V,
6
pF
V
I
=
0V or V
CC
C
I/O
Output Capacitance
V
I
=
0V, or V
CC
,
7
pF
V
CC
=
1.8V, 2.5V or 3.3V
C
PD
Power Dissipation Capacitance
V
I
=
0V or V
CC
, f
=
10 MHz
20
pF
V
CC
=
1.8V, 2.5V or 3.3V
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