July 1993
Revised April 1999
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VH
C12
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A Dual
Ret
r
i
ggerabl
e
M
ono
stabl
e Mul
t
i
v
ib
rat
o
r
1999 Fairchild Semiconductor Corporation
DS011621.prf
www.fairchildsemi.com
74VHC123A
Dual Retriggerable Monostable Multivibrator
General Description
The VHC123A is an advanced high speed CMOS
Monostable Multivibrator fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. Each multivibrator features
both a negative, A, and a positive, B, transition triggered
input, either of which can be used as an inhibit input. Also
included is a clear input that when taken low resets the
one-shot. The VHC123A can be triggered on the positive
transition of the clear while A is held low and B is held high.
The output pulse width is determined by the equation:
PW
=
(R
x
)(C
x
); where PW is in seconds, R is in ohms, and
C is in farads.
Limits for R
x
and C
x
are:
External capacitor, C
x
No limit
External resistors, R
x
V
CC
=
2.0V, 5 k
min
V
CC
>
3.0V, 1 k
min
An input protection circuit ensures that 0 to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed:
t
PD
=
8.1 ns (typ) at T
A
=
25
C
s
Low Power Dissipation:
I
CC
=
4
A (Max) at T
A
=
25
C
s
Active State: I
CC
=
600
A (Max) at T
A
=
25
C
s
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Pin and function compatible with 74HC123A
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74VHC123AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC123ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC123AMTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC123AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
=
HIGH-to-LOW Transition
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition
X
=
Don't Care
Block Diagrams
Note A: C
x
, R
x
, D
x
are external Capacitor, Resistor, and Diode, respectively.
Note B: External clamping diode, D
x
;
External capacitor is charged to V
CC
level in the wait state, i.e. when no trigger is applied.
If the supply voltage is turned off, C
x
discharges mainly through the internal (parasitic) diode. If C
x
is sufficiently large and V
CC
drops rapidly, there will be
some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and V
CC
drops slowly,
the in rush current is automatically limited and damage to the IC is avoided.
The maximum value of forward current through the parasitic diode is
20 mA. In the case of a large Cx, the limit of fall time of the supply voltage is deter-
mined as follows:
t
f
(V
CC
-
0.7) C
x
/20 mA
(t
f
is the time between the supply voltage turn off and the supply voltage reaching 0.4 V
CC
)
In the event a system does not satisfy the above condition, an external clamping diode (D
x
) is needed to protect the IC from rush current.
System Diagram
Pin Names
Description
A
Trigger Inputs (Negative Edge)
B
Trigger Inputs (Positive Edge)
CLR
Reset Inputs
C
x
External Capacitor
R
x
External Resistor
Q, Q
Outputs
Inputs
Outputs
Function
A
B
CLR
Q
Q
H
H
Output Enable
X
L
H
L
H
Inhibit
H
X
H
L
H
Inhibit
L
H
Output Enable
L
H
Output Enable
X
X
L
L
H
Reset
3
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Timing Chart
Functional Description
1. Stand-by State
The external capacitor (C
x
) is fully charged to V
CC
in
the Stand-by State. That means, before triggering, the
Q
P
and Q
N
transistors which are connected to the R
x
/
C
x
node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply current
is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling signal;
and third, where the A input is LOW and the B input is
HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C
1
and
C
2
start operating, and Q
N
is turned on. The external
capacitor discharges through Q
N
. The voltage level at
the R
x
/C
x
node drops. If the R
x
/C
x
voltage level falls to
the internal reference voltage V
ref
L, the output of C
1
becomes LOW. The flip-flop is then reset and Q
N
turns
off. At that moment C
1
stops but C
2
continues operat-
ing.
After Q
N
turns off, the voltage at the R
x
/C
x
node starts
rising at a rate determined by the time constant of
external capacitor C
x
and resistor R
x
.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of R
x
/C
x
changes from falling
to rising. When R
x
/C
x
reaches the internal reference
voltage V
ref
H, the output of C
2
becomes LOW, the out-
put Q goes LOW and C
2
stops its operation. That
means, after triggering, when the voltage level of the
R
x
/C
x
node reaches V
ref
H, the IC returns to its
MONOSTABLE state.
With large values of C
x
and R
x
, and ignoring the dis-
charge time of the capacitor and internal delays of the
IC, the width of the output pulse, t
W
(OUT), is as fol-
lows:
t
W
(OUT)
=
1.0 C
x
R
x
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging C
x
. The voltage level of the R
x
/C
x
node then falls to V
ref
L level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by C
x
and R
x
.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd trig-
ger, t
RR
(Min), depends on V
CC
and C
x
.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q out-
put is held LOW and the trigger control F/F is reset.
Also, Q
p
turns on and C
x
is charged rapidly to V
CC
.
This means if CLR is set LOW, the IC goes into a wait
state.
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommended operation outside data book speci-
fications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
Note 3: The maximum allowable values of C
x
and R
x
are a function of the
leakage of capacitor C
x
, the leakage of the device, and leakage due to
board layout and surface resistance. Susceptibility to externally induced
noise signals may occur for R
x
>
1 M
.
DC Electrical Characteristics
Note 4: Per Circuit
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5 to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/Current (I
CC
)
50 mA
Storage Temperature (T
STG
)
-
65
C to 150
C
Lead Temperature (T
L
)
Soldering, 10 seconds
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature
(T
opr
)
-
40
to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
(CLR only)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
External Capacitor - C
x
No Limitation (Note 3) F
External Resistor - R
x
>
5 k
(Note 3) (V
CC
=
2.0V)
>
1 k
(Note 3) (V
CC
>
3.0V)
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
to 85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.50
1.50
V
Input Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level
2.0
0.50
0.50
V
Input Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
IN
=
V
IH
I
OH
=
-
50
A
Output Voltage
3.0
2.9
3.0
2.9
V
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
50
A
Output Voltage
3.0
0.0
0.1
0.1
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
IN
R
x
/C
x
Terminal
5.5
0.25
2.50
A
V
IN
=
V
CC
or GND
Off-State Current
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
I
CC
Active--State 3.0
160
250
280
V
IN
=
V
CC
or GND
(Note 4)
4.5
380
500
650
A
R
x
/C
x
=
0.5 V
CC
Supply Current
5.5
560
750
975
5
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AC Electrical Characteristics
(Note 5)
Note 5: Refer to Timing Chart.
Note 6: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation:
I
CC
(opr.)
=
C
PD
*V
CC
*f
IN
+
I
CC
1
*Duty/100
+
I
CC
/2 (per Circuit)
I
CC
1
: Active Supply Current
Duty:%
AC Operating Requirement
(Note 7)
Note 7: Refer to Timing Chart.
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
t
PHL
Propagation Delay Time
3.3
0.3
13.4
20.6
1.0
24.0
ns
C
L
=
15 pF
(A, BQ, Q)
15.9
24.1
1.0
27.5
C
L
=
50 pF
5.0
0.5
8.1
12.0
1.0
14.0
ns
C
L
=
15 pF
9.6
14.0
1.0
16.0
C
L
=
50 pF
t
PLH
t
PHL
Propagation Delay Time
3.3
0.3
14.5
22.4
1.0
26.0
ns
C
L
=
15 pF
(CLR Trigger--Q, Q \)
17.0
25.9
1.0
29.5
C
L
=
50 pF
5.0
0.5
8.7
12.9
1.0
15.0
ns
C
L
=
15 pF
10.2
14.9
1.0
17.0
C
L
=
50 pF
t
PLH
t
PHL
Propagation Delay Time
3.3
0.3
10.3
15.8
1.0
18.5
ns
C
L
=
15 pF
(CLR--Q, Q)
12.8
19.3
1.0
22.0
C
L
=
50 pF
5.0
0.5
6.3
9.4
1.0
11.0
ns
C
L
=
15 pF
7.8
11.4
1.0
13.0
C
L
=
50 pF
t
WOUT
Output Pulse Width
3.3
0.3
160
240
300
ns
C
L
=
50 pF C
x
=
28 pF
5.0
0.5
133
200
240
R
x
=
2 k
3.3
0.3
90
100
110
90
110
s
C
L
=
50 pF C
x
=
0.01
F
5.0
0.5
90
100
110
90
110
R
x
=
10 k
3.3
0.3
0.9
1.0
1.1
0.9
1.1
ms
C
L
=
50 pF C
x
=
0.1
F
5.0
0.5
0.9
1.0
1.1
0.9
1.1
R
x
=
10 k
t
WOUT
Output Pulse Width Error
Between Circuits
1
%
(In same Package)
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation
73
pF
(Note 6)
Capacitance
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
W
(L)
Minimum Trigger
3.3
5.0
5.0
ns
t
W
(H)
Pulse Width
5.0
5.0
5.0
t
W
(L)
Minimum Clear
3.3
5.0
5.0
ns
Pulse Width
5.0
5.0
5.0
t
RR
Minimum
3.3
0.3
60
ns
R
x
=
1 k
Retrigger Time
5.0
0.5
39
C
X
=
100 pF
3.3
1.5
s
R
x
=
1 k
5.0
1.2
C
X
=
0.01
F
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Device Characteristics
t
wout
*C
x
Characteristics (typ)
t
RR
*V
CC
Characteristics (typ)
Output Pulse Width Constant K-Supply Voltage
(Typical)
Input Equivalent Circuit
7
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Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7
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VH
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A Dual
Ret
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i
ggerabl
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M
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stabl
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i
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LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
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