March 1993
Revised March 1999
7
4
VH
C39
3
Dual
4-
Bit
Bi
nary
Count
er
1999 Fairchild Semiconductor Corporation
DS011571.prf
www.fairchildsemi.com
74VHC393
Dual 4-Bit Binary Counter
General Description
The VHC393 is an advanced high speed CMOS 4-bit
Binary Counter fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. It contains two independent counter cir-
cuits in one package, so that counting or frequency division
of 8 binary bits can be achieved with one IC. This device
changes state on the negative going transition of the
CLOCK pulse. The counter can be reset to "0" (Q
0
Q
3
=
"L") by a HIGH at the CLEAR input regardless of other
inputs.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: f
MAX
=
170 MHz (typ) at T
A
=
25
C
s
Low power dissipation: I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Pin and function compatible with 74HC393
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74VHC393M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
74VHC393SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC393MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC393N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
CLR1, CLR2
Clear Inputs
CP
1
, CP
2
Clock Pulse Inputs
QA, QB, QC, QD
Outputs
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2
74
V
HC393
Truth Table
X: Don't Care
System Diagram
Timing Chart
Inputs
Outputs
CP
CLR
QA
QB
QC
QD
X
H
L
L
L
L
L
Count Up
L
No Change
3
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7
4
VH
C39
3
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
75 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.50
1.50
V
Input Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level
2.0
0.50
0.50
V
Input Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
V
IN
=
V
IH
I
OH
=
-
50
A
Output Voltage
3.0
2.9
3.0
2.9
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW
Level 2.0
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
50
A
Output Voltage
3.0
0.0
0.1
0.1
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
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4
74
V
HC393
AC Electrical Characteristics
Note 3: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load Average
operating current can be obtained by the equation: I
CC
(opr.)
=
C
PD
*V
CC
*f
IN
+
I
CC/2
(per Counter)
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation
3.3
0.3
8.6
13.2
1.0
15.5
ns
C
L
=
15 pF
t
PHL
Delay Time
11.1
16.7
1.0
19.0
C
L
=
50 pF
(CP -QA)
5.0
0.5
5.8
8.5
1.0
10.0
ns
C
L
=
15 pF
7.3
10.5
1.0
12.0
C
L
=
50 pF
t
PLH
Propagation
3.3
0.3
10.2
15.8
1.0
18.5
ns
C
L
=
15 pF
t
PHL
Delay Time
12.7
19.3
1.0
22.0
C
L
=
50 pF
(CP -QB)
5.0
0.5
6.8
9.8
1.0
11.5
ns
C
L
=
15 pF
8.3
11.8
1.0
13.5
C
L
=
50 pF
t
PLH
Propagation
3.3
0.3
11.7
18.0
1.0
21.0
ns
C
L
=
15 pF
t
PHL
Delay Time
14.2
21.5
1.0
24.5
C
L
=
50 pF
(CP -QC)
5.0
0.5
7.7
11.2
1.0
13.0
ns
C
L
=
15 pF
9.2
13.2
1.0
15.0
C
L
=
50 pF
t
PLH
Propagation
3.3
0.3
13.0
19.7
1.0
23.0
ns
C
L
=
15 pF
t
PHL
Delay Time
15.5
23.2
1.0
26.5
C
L
=
50 pF
(CP -QD)
5.0
0.5
8.5
12.5
1.0
14.5
ns
C
L
=
15 pF
10.0
14.5
1.0
16.5
C
L
=
50 pF
t
PLH
Propagation
3.3
0.3
7.9
12.3
1.0
14.5
ns
C
L
=
15 pF
t
PHL
Delay Time
10.4
15.8
1.0
18.0
C
L
=
50 pF
(CLR-Q
n
)
5.0
0.5
5.4
8.1
1.0
9.5
ns
C
L
=
15 pF
6.9
10.1
1.0
11.5
C
L
=
50 pF
f
MAX
Maximum
3.3
0.3
75
120
65
MHz
C
L
=
15 pF
Clock
45
65
35
C
L
=
50 pF
5.0
0.5
125
170
105
C
L
=
15 pF
85
115
75
C
L
=
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation
23
pF
(Note 3)
Capacitance
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Typ
Guaranteed Minimum
t
W
(L)
Minimum Pulse
3.3
0.3
5.0
5.0
ns
t
W
(H)
Width (CP)
5.0
0.5
5.0
5.0
t
W
(H)
Minimum Pulse
3.3
0.3
5.0
5.0
ns
Width (CLR)
5.0
0.5
5.0
5.0
t
REM
Minimum Removal
3.3
0.3
5.0
5.0
ns
Time
5.0
0.5
4.0
4.0
5
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7
4
VH
C39
3
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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6
74
V
HC393
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7
4
VH
C39
3
Dual
4-
Bit
Bi
nary
Count
er
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
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