August 1993
Revised April 1999
7
4
VH
C40
40 12-
Sta
ge Bi
nary
Counte
r
1999 Fairchild Semiconductor Corporation
DS011641.prf
www.fairchildsemi.com
74VHC4040
12-Stage Binary Counter
General Description
The VHC4040 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC4040 is a 12-stage counter which incre-
ments on the negative edge of the input clock and all
outputs are reset to a low level by applying a logical high
on the reset input. An input protection circuit insures that
0V to 7V can be applied to the inputs without regard to the
supply voltage. This device can be used to interface 5V to
3V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Features
s
High speed; f
MAX
=
210 MHz at V
CC
=
5V
s
Low power dissipation: I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Wide operating voltage range: V
CC
(opr)
=
2V
-
5.5V
s
Low noise: V
OLP
=
0.8V (max)
s
Pin and function compatible with 74HC4040
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74VHC4040M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC4040MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4040N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
Q
0
Q
11
Flip-Flop Outputs
CP
Negative Edged Triggered Clock
MR
Master Reset
3
www.fairchildsemi.com
7
4
VH
C40
40
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
75 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input
2.0
1.50
1.50
V
Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input
2.0
0.50
0.50
V
Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output
2.0
1.9
2.0
1.9
V
V
IN
=
V
IH
or V
IL
I
OH
=
-
50
A
Voltage
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
3.0
2.58
2.48
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW Level Output
2.0
0.0
0.1
0.1
V
V
IN
=
V
IH
or V
IL
I
OL
=
50
A
Voltage
3.0
0.0
0.1
0.1
4.5
0.0
0.1
0.1
3.0
0.36
0.44
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
www.fairchildsemi.com
4
74VHC4040
AC Electrical Characteristics
Note 3: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr)
=
C
PD
* V
CC
* f
N
+
I
CC
.
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay Time
3.3
0.3
7.5
11.9
1.0
14.0
ns
C
L
=
15 pF
t
PHL
to Q
1
10.0
15.4
1.0
17.5
C
L
=
50 pF
5.0
0.5
4.8
7.3
1.0
8.5
ns
C
L
=
15 pF
6.3
9.3
1.0
10.5
C
L
=
50 pF
t
PLH
Propagation Delay Time
3.3
0.3
ns
C
L
=
15 pF
t
PHL
between Stages from
2.4
4.4
1.0
5.0
C
L
=
50 pF
Q
n
to Q
n
+
1
5.0
0.5
ns
C
L
=
15 pF
1.6
3.1
1.0
3.5
C
L
=
50 pF
t
PHL
Propagation Delay Time
3.3
0.3
8.3
12.8
1.0
15.0
ns
C
L
=
15 pF
MRQ
n
10.8
16.3
1.0
18.5
C
L
=
50 pF
5.0
0.5
5.6
8.6
1.0
10.0
ns
C
L
=
15 pF
7.1
10.6
1.0
12.0
C
L
=
50 pF
f
MAX
Maximum Clock
3.3
0.3
90
140
75
MHz
C
L
=
15 pF
Frequency
55
80
50
C
L
=
50 pF
5.0
0.5
150
210
125
MHz
C
L
=
15 pF
95
125
80
C
L
=
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation Capacitance
21
pF
(Note 3)
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Typ
Guaranteed Minimum
t
w
(L)
Minimum Pulse Width
3.3
0.3
5.0
5.0
ns
t
w
(H)
(CP)
5.0
0.5
5.0
5.0
t
w
(L)
Minimum Pulse Width
3.3
0.3
5.0
5.0
ns
(MR)
5.0
0.5
5.0
5.0
t
REC
Minimum Removal Time
3.3
0.3
5.0
5.0
ns
(MR)
5.0
0.5
5.0
5.0
5
www.fairchildsemi.com
7
4
VH
C40
40
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
PDF 
ZIP