1
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
July 2000
2000 Fairchild Semiconductor International
FM93C66
4096-Bit Serial CMOS EEPROM
(MICROWIRETM Synchronous Bus)
General Description
FM93C66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the FM93C66 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
"LZ" and "L" versions of FM93C66 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
Functional Diagram
Features
I Wide V
CC
2.7V - 5.5V
I Typical active current of 200A
10
A standby current typical
1
A standby current typical (L)
0.1
A standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
INSTRUCTION
REGISTER
ADDRESS
REGISTER
EEPROM ARRAY
READ/WRITE AMPS
DATA IN/OUT REGISTER
16 BITS
DECODER
16
16
DATA OUT BUFFER
CS
SK
DI
DO
V
SS
V
CC
2
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N)
8Pin SO (M8) and 8Pin TSSOP (MT8)
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
NC
No Connect
V
CC
Power Supply
NOTE:
Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the V
CC
applied to the device. This will ensure proper operation.
Ordering Information
FM
93
C
XX
LZ
E
XXX
Letter Description
Package
N
8-pin DIP
M8
8-pin SO
MT8
8-pin TSSOP
Temp. Range
None
0 to 70
C
V
-40 to +125
C
E
-40 to +85
C
Voltage Operating Range
Blank
4.5V to 5.5V
L
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1
A Standby Current
Density
66
4096 bits
C
CMOS
CS
Data protect and sequential
read
Interface
93
MICROWIRE
Fairchild Memory Prefix
V
CC
NC
GND
CS
SK
DI
DO
1
2
3
4
8
7
6
5
NC
3
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
-65
C to +150C
All Input or Output Voltages
+6.5V to -0.3V
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
+300
C
ESD rating
2000V
Operating Conditions
Ambient Operating Temperature
FM93C66
0
C to +70C
FM93C66E
-40
C to +85C
FM93C66V
-40
C to +125C
Power Supply (V
CC
)
4.5V to 5.5V
DC and AC Electrical Characteristics
V
CC
= 4.5V to 5.5V unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
I
CCA
Operating Current
CS = V
IH
, SK=1.0 MHz
1
mA
I
CCS
Standby Current
CS = V
IL
50
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
-1
A
I
OL
Output Leakage
(Note 2)
V
IL
Input Low Voltage
-0.1
0.8
V
V
IH
Input High Voltage
2
V
CC
+1
V
OL1
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH1
Output High Voltage
I
OH
= -400
A
2.4
V
OL2
Output Low Voltage
I
OL
= 10
A
0.2
V
V
OH2
Output High Voltage
I
OH
= -10
A
V
CC
- 0.2
f
SK
SK Clock Frequency
(Note 3)
1
MHz
t
SKH
SK High Time
0
C to +70C
250
ns
-40
C to +125C
300
t
SKL
SK Low Time
250
ns
t
CS
Minimum CS Low Time
(Note 4)
250
ns
t
CSS
CS Setup Time
50
ns
t
DH
DO Hold Time
70
ns
t
DIS
DI Setup Time
100
ns
t
CSH
CS Hold Time
0
ns
t
DIH
DI Hold Time
20
ns
t
PD
Output Delay
500
ns
t
SV
CS to Status Valid
500
ns
t
DF
CS to DO in Hi-Z
CS = V
IL
100
ns
t
WP
Write Cycle Time
10
ms
4
www.fairchildsemi.com
FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
-65
C to +150C
All Input or Output Voltages
+6.5V to -0.3V
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
+300
C
ESD rating
2000V
Operating Conditions
Ambient Operating Temperature
FM93C66L/LZ
0
C to +70C
FM93C66LE/LZE
-40
C to +85C
FM93C66LV/LZV
-40
C to +125C
Power Supply (V
CC
)
2.7V to 5.5V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for V
CC
= 4.5V to 5.5V.
Symbol
Parameter
Conditions
Min
Max
Units
I
CCA
Operating Current
CS = V
IH
, SK=250 KHz
1
mA
I
CCS
Standby Current
CS = V
IL
L
10
A
LZ (2.7V to 4.5V)
1
A
I
IL
Input Leakage
V
IN
= 0V to V
CC
1
A
I
OL
Output Leakage
(Note 2)
V
IL
Input Low Voltage
-0.1
0.15V
CC
V
V
IH
Input High Voltage
0.8V
CC
V
CC
+1
V
OL
Output Low Voltage
I
OL
= 10
A
0.1V
CC
V
V
OH
Output High Voltage
I
OH
= -10
A
0.9V
CC
f
SK
SK Clock Frequency
(Note 3)
0
250
KHz
t
SKH
SK High Time
1
s
t
SKL
SK Low Time
1
s
t
CS
Minimum CS Low Time
(Note 4)
1
s
t
CSS
CS Setup Time
0.2
s
t
DH
DO Hold Time
70
ns
t
DIS
DI Setup Time
0.4
s
t
CSH
CS Hold Time
0
ns
t
DIH
DI Hold Time
0.4
s
t
PD
Output Delay
2
s
t
SV
CS to Status Valid
1
s
t
DF
CS to DO in Hi-Z
CS = V
IL
0.4
s
t
WP
Write Cycle Time
15
ms
Capacitance T
A
= 25
C, f = 1 MHz or
250 KHz (Note 5)
Symbol
Test
Typ
Max
Units
C
OUT
Output Capacitance
5
pF
C
IN
Input Capacitance
5
pF
Note 1:
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Note 3:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
V
IL
/V
IH
V
IL
/V
IH
V
OL
/V
OH
I
OL
/I
OH
Input Levels
Timing Level
Timing Level
2.7V
V
CC
5.5V
0.3V/1.8V
1.0V
0.8V/1.5V
10A
(Extended Voltage Levels)
4.5V
V
CC
5.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (C
L
= 100 pF)
5
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Pin Description
Chip Select (CS)
This is an active high input pin to FM93C66 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array, a set of 7 instructions are implemented on FM93C66.
The format of each instruction is listed under Table 1.
Instruction
Each of the 7 instructions is explained under individual instruction
descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be "1" for a valid cycle
to begin. Any number of preceding "0" can be clocked into the
device before clocking a "1".
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Address Field
This is an 8-bit field and should immediately follow the Opcode bits.
In FM93C66, all 8 bits are used for address decoding during READ,
WRITE and ERASE instructions. During all other instructions, the
MSB 2 bits are used to decode instruction (along with Opcode bits).
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
Table 1. Instruction set
Instruction
Start Bit
Opcode Field
Address Field
Data Field
READ
1
10
A7
A6
A5
A4
A3
A2
A1
A0
WEN
1
00
1
1
X
X
X
X
X
X
WRITE
1
01
A7
A6
A5
A4
A3
A2
A1
A0
D15-D0
WRALL
1
00
0
1
X
X
X
X
X
X
D15-D0
WDS
1
00
0
0
X
X
X
X
X
X
ERASE
1
11
A7
A6
A5
A4
A3
A2
A1
A0
ERAL
1
00
1
0
X
X
X
X
X
X
6
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit ("1") should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 8-bit address information
should be issued. For certain instructions, some of these 8 bits are
don't care values (can be "0" or "1"), but they should still be issued.
Following the address information, depending on the instruction
(WRITE and WRALL), 16-Bit data is issued. Otherwise, depend-
ing on the instruction (READ), the device starts to drive the output
data on the DO line. Other instructions perform certain control
functions and do not deal with data bits. The Microwire cycle ends
when the CS signal is brought low. However during certain
instructions, falling edge of the CS signal initiates an internal cycle
(Programming), and the device remains busy till the completion of
the internal cycle. Each of the 7 instructions is explained in detail
in the following sections.
1) Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. Refer
Read cycle diagram.
2) Write Enable (WEN)
When V
CC
is applied to the part, it "powers up" in the Write Disable
(WDS) state. Therefore, all programming operations must be
preceded by a Write Enable (WEN) instruction. Once a Write
Enable instruction is executed, programming remains enabled
until a Write Disable (WDS) instruction is executed or V
CC
is
completely removed from the part. Input information (Start bit,
Opcode and Address) for this WEN instruction should be issued
as listed under Table1. The device becomes write-enabled at the
end of this cycle when the CS signal is brought low. Execution of
a READ instruction is independent of WEN instruction. Refer
Write Enable cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only when
device is write-enabled (Refer WEN instruction).
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after t
CS
interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer
Write cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when device is write-enabled (Refer
WEN instruction).
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer
Write All
cycle diagram.
5) Write Disable (WDS)
Write Disable (WDS) instruction disables all programming opera-
tions and should follow all programming operations. Executing this
instruction after a valid write instruction would protect against
accidental data disturb due to spurious noise, glitches, inadvertent
writes etc. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. The
device becomes write-disabled at the end of this cycle when the CS
signal is brought low.
Execution of a READ instruction is indepen-
dent of WDS instruction. Refer
Write Disable cycle diagram.
6) Erase (ERASE)
The ERASE instruction will program all bits in the specified
location to a logical "1" state. Input information (Start bit, Opcode
and Address) for this WDS instruction should be issued as listed
under Table1. After inputting the last bit of data (A0 bit), CS signal
must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming
cycle. It takes t
WP
time (Refer appropriate DC and AC Electrical
Characteristics table) for the internal programming cycle to finish.
During this time, the device remains busy and is not ready for
another instruction. Status of the internal programming can be
polled as described under WRITE instruction description. While
the device is busy, it is recommended that no new instruction be
issued. Refer
Erase cycle diagram.
7) Erase All (ERAL)
7
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
The Erase all instruction will program all locations to a logical "1"
state. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. After
inputting the last bit of data (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer
Erase
All cycle diagram.
Note:
The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
instruction prior to the "WRITE" or "WRITE ALL" instruction, respectively. The
"ERASE" and "ERASE ALL" instructions are included to maintain compatibility with
earlier technology EEPROMs.Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is `cleared'
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer
Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchild's MICROWIRETM EE-
PROM.
8
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
t
CSS
SYNCHRONOUS DATA TIMING
CS
SK
DI
DO (Data Read)
DO (Status Read)
Valid Status
t
DIS
t
DIH
t
PD
t
DH
t
SV
t
SKH
t
SKL
t
CSH
t
DF
t
DF
t
PD
Valid
Input
Valid
Input
Valid
Output
Valid
Output
CS
SK
DI
DO
High - Z
D u m my
B i t
1
1
0
A7
A6
A1
A0
0
D15
D1
D0
;;;;;;;;;;;;;;
;;;;;;;;;;;;;;
t
CS
;;;
;;;
READ CYCLE (READ)
A d d r e s s
B i t s ( 8 )
S t a r t
B i t
O p c o d e
B i t s ( 2 )
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > U s e r d e f i n e d
Timing Diagrams
A d d r e s s
B i t s ( 8 )
CS
SK
DI
DO
High - Z
WRITE ENABLE CYCLE (WEN)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
O p c o d e
B i t s ( 2 )
1
0
0
A7
A6
A1
A0
t
CS
9
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Timing Diagrams
(Continued)
A d d r e s s
B i t s ( 8 )
CS
SK
DI
DO
High - Z
WRITE DISABLE CYCLE (WDS)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > 0 - 0 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
O p c o d e
B i t s ( 2 )
1
0
0
A7
A6
A1
A0
t
CS
A d d r e s s
B i t s ( 8 )
D a t a
B i t s ( 1 6 )
CS
SK
DI
DO
High - Z
t
CS
WRITE CYCLE (WRITE)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > U s e r d e f i n e d
D a t a b i t s p a t t e r n - > U s e r d e f i n e d
O p c o d e
B i t s ( 2 )
1
0
1
A7
A6
A1
A0
D15
D14
D1
D0
Busy
Ready
t
WP
A d d r e s s
B i t s ( 8 )
D a t a
B i t s ( 1 6 )
CS
SK
DI
DO
High - Z
t
CS
WRITE ALL CYCLE (WRALL)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > 0 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )
D a t a b i t s p a t t e r n - > U s e r d e f i n e d
O p c o d e
B i t s ( 2 )
1
0
0
A7
A6
A1
A0
D15
D14
D1
D0
Busy
Ready
t
WP
10
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Timing Diagrams
(Continued)
CS
SK
DI
DO
High - Z
High - Z
CLEARING READY STATUS
S t a r t
B i t
N o t e : T h i s S t a r t b i t c a n a l s o b e p a r t o f a n ex t i n s t r u c t i o n . H e n c e t h e c y c l e
c a n b e c o n t i nu e d ( i n s t e a d o f g e t t i n g t e r m i n a t e d , a s s h ow n ) a s i f a n ew
i n s t r u c t i o n i s b e i n g i s s u e d .
Busy
Ready
A d d r e s s
B i t s ( 8 )
CS
SK
DI
DO
High - Z
t
CS
ERASE CYCLE (ERASE)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > U s e r d e f i n e d
O p c o d e
B i t s ( 2 )
1
1
1
A7
A6
A1
A0
Busy
Ready
t
WP
A d d r e s s
B i t s ( 8 )
CS
SK
DI
DO
High - Z
t
CS
ERASE ALL CYCLE (ERAL)
S t a r t
B i t
9 3 C 6 6 :
A d d r e s s b i t s p a t t e r n - > 1 - 0 - x - x - x - x - x - x
; ( x - > D o n ' t C a r e , c a n b e 0 o r 1 )
O p c o d e
B i t s ( 2 )
1
0
0
A7
A6
A1
A0
Busy
Ready
t
WP
11
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)
Package Number M08A
Physical Dimensions
inches (millimeters) unless otherwise noted
1
2
3 4
8
7
6 5
0.189 - 0.197
(4.800 - 5.004)
0.228 - 0.244
(5.791 - 6.198)
Lead #1
IDENT
Seating
Plane
0.004 - 0.010
(0.102 - 0.254)
0.014 - 0.020
(0.356 - 0.508)
0.014
(0.356)
Typ.
0.053 - 0.069
(1.346 - 1.753)
0.050
(1.270)
Typ
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
8 Max, Typ.
All leads
0.150 - 0.157
(3.810 - 3.988)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.004
(0.102)
All lead tips
0.010 - 0.020
(0.254 - 0.508)
x 45
12
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
Physical Dimensions
inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
0.123 - 0.128
(3.13 - 3.30)
0.246 - 0.256
(6.25 - 6.5)
1
4
8
5
0.169 - 0.177
(4.30 - 4.50)
(7.72) Typ
(4.16) Typ
(1.78) Typ
(0.42) Typ
(0.65) Typ
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
0.0433
(1.1)
Max
0.0075 - 0.0118
(0.19 - 0.30)
Pin #1 IDENT
0.0035 - 0.0079
0-8
0.020 - 0.028
(0.50 - 0.70)
0.0075 - 0.0098
(0.19 - 0.25)
Seating
plane
Gage
plane
See detail A
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
Land pattern recommendation
DETAIL A
Typ. Scale: 40X
13
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FM93C66 Rev. C.1
FM93C66 4096-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Package Number N08E
0.373 - 0.400
(9.474 - 10.16)
0.092
(2.337)
DIA
+
1
2
3
4
8
7
6
5
0.250 - 0.005
(6.35 0.127)
8
7
0.032 0.005
(0.813 0.127)
Pin #1
Option 2
RAD
1
0.145 - 0.200
(3.683 - 5.080)
0.130 0.005
(3.302 0.127)
0.125 - 0.140
(3.175 - 3.556)
0.020
(0.508)
Min
0.018 0.003
(0.457 0.076)
90 4
Typ
0.100 0.010
(2.540 0.254)
0.040
(1.016)
0.039
(0.991)
Typ.
20 1
0.065
(1.651)
0.050
(1.270)
0.060
(1.524)
Pin #1 IDENT
Option 1
0.280 MIN
0.300 - 0.320
(7.62 - 8.128)
0.030
(0.762)
MAX
0.125
(3.175)
DIA
NOM
0.009 - 0.015
(0.229 - 0.381)
0.045 0.015
(1.143 0.381)
0.325
+0.040
-0.015
8.255
+1.016
-0.381
95 5
0.090
(2.286)
(7.112)
IDENT
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor
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